Использование открытых кодов для расширения возможностей платформы MIPSfpga

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    16-Apr-2017

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  • XII CEE-SECR / 2829 ,

    MIPSfpga

    ..

    1/19

  • . . , MIPS- (AKA ).

    Antony Pavlov :

    I linux;

    I barebox (U-Boot v2);

    I qemu;

    I openocd.

    . https://www.openhub.net/accounts/antonynpavlov

    2/19

    mailto:antony@niisi.msk.rumailto:antonynpavlov@gmail.comhttps://www.openhub.net/accounts/antonynpavlov

  • MIPSfpga ( 2015 )

    I Verilog MIPS microAptiv UP /;

    I ;

    I ( ; bare-metal ).

    3/19

  • opencores.org

    opencores.org opensource IP-.

    4/19

  • myMIPSfpga (- 2015 )

    myMIPSfpga myMIPSfpga open source IP- opencores.org.2mm

    :

    I https://github.com/MIPSfpga/myMIPSfpga

    5/19

    https://github.com/MIPSfpga/myMIPSfpga

  • myMIPSfpga

    6/19

  • myMIPSfpga:

    MIPSfpga !

    !

    , MIPSfpga (. myMIPSfpga).

    ...

    7/19

  • myMIPSfpga:

    :

    I , ;

    I NDA;

    I ;

    I ;

    I open sourceIP-.

    7/19

  • myMIPSfpga:

    open source !

    7/19

  • MIPSfpga SoC ( 2015 )

    I AXI IP- XilinxI INTC;I DDR2;I UART;I Ethernet;I I2C;I GPIO.

    I : bare-metal Linux (!); MIPSfpga SoC mainline linux!

    8/19

  • MIPSfpga SoC

    :

    I MIPSfpga;

    I IP- Xilinx.9/19

  • MIPSfpga SoC

    Xilinx.

    9/19

  • MIPSfpga

    I MIPSfpga ;

    I ;

    I MIPSfpga SoC:I IP- Xilinx ;I Xilinx.

    10/19

  • MIPSfpga Getting Started Guide

    (Version 1.3, April 5, 2016)

    Terasic DE2-115 Digilent Nexys4 DDR$595 $320

    (Academic $309) (Academic $159)

    11/19

  • marsohod.org

    I ();

    I (1500 4200 10500 .) Altera;

    I Altera;

    I Verilog;

    I ;

    I .

    12/19

  • 3

    MAX10 10M5050K LE

    1600 Kbits10500 .

    MIPSfpga Getting Started 24K LE.

    13/19

  • Open source:

    I Debian mips-linux-gnu- toolchain ( Codescape MIPSSDK);

    I qemu;

    I Icarus Verilog, gtkwave (* ModelSim);

    14/19

  • Open source:

    I mips32r1 MIPSfpga;

    I Wishbone IP- opencores AXI IP- Xilinx;

    I Wishbone fusesoc;

    I .

    15/19

  • 'mips32r1'

    MIPS32Release 1. Grant Ayers eXtensible Utah Multicore (XUM) 2010-2012 .

    OpenCores github:

    I https://github.com/grantae/mips32r1_core

    16/19

    https://github.com/grantae/mips32r1_core

  • 'mips32r1'

    I single-issue in-order 5-stage pipeline;

    I MMU;

    I -;

    I .

    MIPS32r1, 10K LE Altera., Wishbone ...

    16/19

  • fusesoc

    fusesoc Openrisc .

    17/19

  • , myMIPSfpga:

    .

    :

    I https://github.com/open-design/mips32r1_soc_nano

    18/19

    https://github.com/open-design/mips32r1_soc_nano

  • F I N

    19/19

  • BACKUP

    it may be convenient to have some backup/appendix slides ready as asupport for answers to potential questions.

  • I

    I https://github.com/open-design/mips32r1_soc_nano

    I https://github.com/MIPSfpga/myMIPSfpga

    I https://github.com/open-design/quartus-linux-install

    I mips32r1

    I https://github.com/grantae/mips32r1_core

    I fusesoc

    I https://github.com/olofk/fusesoc

    I https://github.com/openrisc/orpsoc-cores

    I IP- opencores.org (> 660 !)

    I https://github.com/fabriziotappero/ip-cores

    https://github.com/open-design/mips32r1_soc_nanohttps://github.com/MIPSfpga/myMIPSfpgahttps://github.com/open-design/quartus-linux-installhttps://github.com/grantae/mips32r1_corehttps://github.com/olofk/fusesochttps://github.com/openrisc/orpsoc-coreshttps://github.com/fabriziotappero/ip-cores

  • DIGILENT: Your order has NOT been processed.

    At this time, we are unable to ship orders toRussia from our US website due to shippingrestrictions beyond our control.

  • terraelectronica.ru

    From: Subject: RE: DL-NEXYS4, DigilentDate: Tue, 16 Jun 2015 09:31:12 +0300

    !

    , .

  • MIPSfpga

    I MIPSfpga Getting Started

    I MIPSfpga Fundamentals

    I MIPSfpga SoC

    I The Connected Microcontroller

    Lab

  • MIPSfpga

    I MIPSfpga Getting StartedI RTL MIPSfpga;I ;I Codescape MIPS SDK;I ; .

    I MIPSfpga FundamentalsI Getting Started: (7SEG display, timer, buzzer, SPILCD);

    I : bare-metal .

  • MIPSfpga Getting Started

    :

    I MIPSfpga;

    I MIPSfpga Getting Started.

  • MIPSfpga Getting Started

    AHB-Lite .

  • MIPSfpga Getting Started

    IP- Verilog.

  • fusesoc + MIPSfpga

  • I Wishbone mips32r1;

    I mips32r1 ;

    I , MIPSfpga SoC;

    I Lattice icestorm (http://www.cliord.at/icestorm/);

    I Xilinx (e.g. fusesoc has Vivadobackend).

    http://www.clifford.at/icestorm/

    Appendix