제 2 장 CPU 의 구조와 기능

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2 CPU . 2.1 CPU 2.2 2.3 2.4 . CPU . (Instruction Fetch) : (Instruction Decode) : . CPU ( ). - PowerPoint PPT Presentation

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  • 2 CPU 2.1 CPU 2.2 2.3 2.4

    Computer Architecture

  • Computer Architecture2-*CPU (Instruction Fetch) : (Instruction Decode) :

    Computer Architecture

  • Computer Architecture2-*CPU () (Data Fetch) :

    (Data Process) :

    (Data Store) :

    Computer Architecture

  • Computer Architecture2-*2.1 CPU (Arithmetic and Logical Unit: ALU) (Register Set) (Control Unit)

    Computer Architecture

  • Computer Architecture2-*CPU ALU : +, -, , : AND, OR, NOT, XOR

    (register set)CPU . CPU ( )

    Computer Architecture

  • Computer Architecture2-*CPU () () , (control signals)

    CPU (internal CPU bus): ALU , .

    Computer Architecture

  • Computer Architecture2-*2.2 (instruction cycle)CPU , CPU (subcycle) (fetch cycle) : CPU (execution cycle) :

    Computer Architecture

  • Computer Architecture2-*

    Computer Architecture

  • Computer Architecture2-* CPU (Program Counter: PC) ( ) (branch) (Accumulator: AC) . CPU ( ) (Instruction Register: IR)

    Computer Architecture

  • Computer Architecture2-* CPU () (Memory Address Register: MAR)PC

    (Memory Buffer Register: MBR)

    Computer Architecture

  • Computer Architecture2-* CPU

    Computer Architecture

  • Computer Architecture2-* 2.2.1 t0 : MAR PC t1 : MBR M[MAR], PC PC + 1 t2 : IR MBR , t0, t1 t2 CPU

    [ ] PC CPU MAR [ ] MBR , PC 1 [ ] MBR IR

    () CPU = 100 ( = 10) : 10 x 3 = 30

    Computer Architecture

  • Computer Architecture2-*

    Computer Architecture

  • Computer Architecture2-*2.2.2 CPU (decode), CPU : CPU I/O : : : -

    Computer Architecture

  • Computer Architecture2-* (operation code)CPU

    (operand) (addr)

    Computer Architecture

  • Computer Architecture2-*[ 1] LOAD addr CPU AC

    t0 : MAR IR(addr) t1 : MBR M[MAR] t2 : AC MBR

    [ ] IR MAR [ ] MBR [ ] AC

    Computer Architecture

  • Computer Architecture2-*[ 2] STA addr AC

    t0 : MAR IR(addr) t1 : MBR AC t2 : M[MAR] MBR

    [ ] MAR [ ] MBR [ ] MBR MAR

    Computer Architecture

  • Computer Architecture2-*[ 3] ADD addr AC , AC

    t0 : MAR IR(addr) t1 : MBR M[MAR] t2 : AC AC + MBR

    [ ] MAR [ ] MBR [ ] AC AC

    Computer Architecture

  • Computer Architecture2-*ADD

    Computer Architecture

  • Computer Architecture2-*[ 4] JUMP addr (addr) (branch)

    t0 : PC IR(addr)

    ( ) PC

    Computer Architecture

  • Computer Architecture2-*

    100 LOAD2501250101 ADD2515251102 STA2512251103 JUMP1708170

    Computer Architecture

  • Computer Architecture2-* ()100 IR 250 AC PC = PC + 1 = 101

    Computer Architecture

  • Computer Architecture2-* () 101 IR AC 251 , AC PC 102

    Computer Architecture

  • Computer Architecture2-* () 102 IR AC 251 PC 103

    Computer Architecture

  • Computer Architecture2-* () 103 IR , IR (170) PC ( 170 )

    Computer Architecture

  • Computer Architecture2-*2.2.3 (interrupt cycle) CPU ,CPU , (interrupt service routine: ISR) .

    Computer Architecture

  • Computer Architecture2-*

    Computer Architecture

  • Computer Architecture2-* CPU

    CPU , (PC ) (stack) PC 7

    Computer Architecture

  • Computer Architecture2-*

    Computer Architecture

  • Computer Architecture2-* t0 : MBR PC t1 : MAR SP, PC ISR t2 : M[MAR] MBR , SP (stack pointer).

    [ ] PC MBR [ ] SP MAR , PC [ ] MBR PC

    Computer Architecture

  • Computer Architecture2-* LOAD 250 , SP = 999, = 650

    100 LOAD 250 101 ADD 251 102 STA 251 103 JUMP 170

    Computer Architecture

  • Computer Architecture2-*

    Computer Architecture

  • Computer Architecture2-* (multiple interrupt) CPU CPU (interrupt flag) = (interrupt disabled) ,

    Computer Architecture

  • Computer Architecture2-* X ISR X Y

    Computer Architecture

  • Computer Architecture2-*2.2.4 (indirect cycle) , (indirect addressing mode) - t0 : MAR IR(addr) t1 : MBR M[MAR] t2 : IR(addr) MBR IR

    Computer Architecture

  • Computer Architecture2-*2.3 (instruction pipelining)CPU CPU

    2- (two-stage instruction pipeline) (fetch stage) (execute stage) ,

    Computer Architecture

  • Computer Architecture2-*2-

    Computer Architecture

  • Computer Architecture2-*2- 2- ( )

    ( )

    Computer Architecture

  • Computer Architecture2-*4- (IF) : (ID) : (decoder) (OF) : (EX) :

    Computer Architecture

  • Computer Architecture2-*4-

    Computer Architecture

  • Computer Architecture2-* = k, = N, , T :T = k + (N - 1), k , (N - 1)

    N T :T = k N

    Computer Architecture

  • Computer Architecture2-* (speedup)

    [] k=4 , N = 100 , Sp = 400/103 = 3.88 N = 1000 , Sp = 4000/1003 = 3.99 N = 10000 , Sp = 40000/10003 = 3.998 N , Sp = 4

    Computer Architecture

  • Computer Architecture2-* = 4, = 1MHz ( = 1 ),

    = 4 1 10 = 4 + (10 - 1) = 13

    = (10 4) / 13 3.08

    Computer Architecture

  • Computer Architecture2-*

    IF OF (memory conflict) (conditional branch) ,

    Computer Architecture

  • Computer Architecture2-*

    Computer Architecture

  • Computer Architecture2-* (prefetch branch target) ,

    (loop buffer) n

    (branch prediction) , (branch history table)

    (delayed branch)

    Computer Architecture

  • Computer Architecture2-* (status register) (condition flag) (S) (Z) 0 , 1(C) (carry) (borrow) 1

    Computer Architecture

  • Computer Architecture2-* ()(E) 1 (V) 1 (I) (interrupt enabled) 0 (interrupt disabled) 1 (P) CPU (supervisor mode) 1 , (user mode) 0

    Computer Architecture

  • Computer Architecture2-*2.4 (instruction set) CPU : CPU : , ( ), : , , :

    Computer Architecture

  • Computer Architecture2-*2.4.1 : , , : , , : AND, OR, NOT exclusive-OR (I/O) : CPU (branch), (subroutine call)

    Computer Architecture

  • Computer Architecture2-* (CALL ) PC (RET )CPU

    Computer Architecture

  • Computer Architecture2-*

    Computer Architecture

  • Computer Architecture2-*CALL/RET CALL X -: t0 : MBR PC t1 : MAR SP, PC X t2 : M[MAR] MBR, SP SP - 1 PC ( ) SP (top of stack) 16, SP SP - 2 RET - t0 : SP SP + 1 t1 : MAR SP t2 : PC M[MAR]

    Computer Architecture

  • Computer Architecture2-*

    Computer Architecture

  • Computer Architecture2-*2.4.2 (Operation Code) (: LOAD, ADD )

    (Operand) CPU , , I/O

    (Next Instruction Address)

    Computer Architecture

  • Computer Architecture2-* (instruction format)(field) : (instruction format) : = : 16-

    Computer Architecture

  • Computer Architecture2-* = 4 24 = 16 5 , 25 = 32

    : : CPU :

    Computer Architecture

  • Computer Architecture2-* 1 , 2 1 = 4 16 2 = 8 : 0 255

    2 , : - 2048 + 2047 , 212 = 4096

    Computer Architecture

  • Computer Architecture2-* 1- (1-address instruction) : [] ADD X ; AC AC + M[X] 2- (two-address instruction) : . [] ADD R1, R2 ; R1 R1 + R2 MOV R1, R2 ; R1 R2 ADD R1, X ; R1 R1 + M[X]

    3- (three-address instruction) : .[] ADD R1, R2, R3 ; R1 R2 + R3

    Computer Architecture

  • Computer Architecture2-*1- 16 1- 5 , : 211 = 2048

    Computer Architecture

  • Computer Architecture2-*2- 2- 16- CPU 5 , 16 . (a) , (b)

    Computer Architecture

  • Computer Architecture2-*3-

    Computer Architecture

  • Computer Architecture2-* ()X = (A + B) x (C - D) ADD : SUB : MUL : DIV : MOV : LOAD : STOR :

    Computer Architecture

  • Computer Architecture2-*1- LOAD A ; AC M[A] ADD B ; AC AC + M[B] STOR T ; M[T] AC LOAD C ; AC M[C] SUB D ; AC AC - M[D] MUL T