Паралелизам на ниво на инструкции и негова употреба

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    24-Jun-2015

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2. ILP ILP ILP Intel Pentium 4 3. ...(. instruction level parallelism - ILP) , 4. ILP , . Intel Pentium , , . Intel Itanium 5. (. pipelining) 6. = ________________________ CPI + CPI CPI - cycles per instruction 7. pipeline RISC 8. CPI CPI - cycles per instruction Ideal pipeline CPI 9. (,, ) 10. () (. true data dependence) (. name dependence) (. control dependence) 11. i1: r3 (r1) op (r2)i2: r5 (r3) op (r4) // i1i3: r6 (r5) op (r4) // i1 RAW (Read After Write) 12. i1: r3 (r1) op (r2)i2: r1 (r4) op (r5) WAR (Write After Read) i1: r3 (r1) op (r2)i2: r3 (r6) op (r7) WAW (Write After Write) 13. if p1 { S1; // S1 e p1, p2};if p2 { S2; // S2 e p2, p1}; 14. ILP ILP ILP Intel Pentium 4 15. 16. for (i=1000; i>0; i=i1)x[i] = x[i] + s; // : 17. 18. overhead- o 7 , 3 4 overhead , for (i=1000; i>0; i=i1) for (i=1000; i>0; i=i4)x[i] = x[i] + s; { x[i] = x[i] + s; x[i-1] = x[i-1] + s; x[i-2] = x[i-2] + s; x[i-3] = x[i-3] + s; } 19. : 3 , 14 (3,5 27 ) 20. / 21. : overhead ( ) o .. 22. ILP ILP ILP Intel Pentium 4 23. : o , o , 24. : o SPEC 34% .. profileinformation 25. : ( SPEC 3% 24%) 26. Branch- prediction buffero o o o 27. N- 0 2n-1 1110 0100 28. - , 29. (m,n) m 2m n- 30. 2- 31. 32. ILP ILP ILP Intel Pentium 4 33. (. instruction issue) , , 34. (in-order issue, in-order execution) => => ?i1: DIV.D F0,F2,F4i2: ADD.D F10,F0,F8i3: SUB.D F12,F8,F14 35. (in-order issue, out-of-order execution) , 36. WAR WAW i1: DIV.D F0,F2,F4 i2: ADD.D F6,F0,F8 i3: SUB.D F8,F10,F14 i4: MUL.D F6,F10,F8 : : 37. - , - 38. RAW WAR WAW DIV.D F0,F2,F4DIV.D F0,F2,F4ADD.D F6,F0,F8ADD.D S,F0,F8S.D F6,0(R1) => S.D S,0(R1)SUB.D F8,F10,F14SUB.D T,F10,F14MUL.D F6,F10,F8 MUL.D F6,F10,F8 39. F&D Unit = Fetch & Decode Unit EUs and RF = Execution Units and Register File 40. MIPS 41. ILP ILP ILP Intel Pentium 4 42. () 43. 3 : , (commit) 44. Reorder buffer (ROB) 4 : Ready storebuffer- 45. 46. 1. - ROB .2. - .3. CDB ROB .4. :1. : , ROB 2. store : , 3. : ROB , 47. ILP ILP ILP Intel Pentium 4 48. (. multiple-issue processors) (. very long instruction word - VLIW) 49. 50. lockstep 51. , , : R1[i]=R1[i]+1Loop: LD R2,0(R1); do{ R2 = R1[i];DADDIU R2,R2,#1; R2++;SD R2,0(R1); R1[i] = R2;DADDIU R1,R1,#8; i++; }BNER2,R3,LOOP; while(R2

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