C1-Tong Quan ASIC

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    08-Jul-2015

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<p>Chng 1: Tng quan ASIC Gii thiu v cng ngh ASIC Phn loi ASIC Cu trc FPGA Cu trc FPGA tng qut Cng ngh lp trnh chip Cu trc FPGA ca mt s hng</p> <p>Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng</p> <p>1</p> <p>Classifications of Integrated Circuits Microprocessors Memory chips (SRAM, DRAM, Flash, ROM, PROM) Standard Components (74LS..) Application-Specific Integrated Circuits Widely used in communication, network, and multimedia systems For a given application, ASIC solutions are normally more effective than the solutions based on running software on microprocessors Many chips in cellular phones, network routers, and game consoles are ASICs Most SoC (Systems-on-a-Chip) chips are ASICsBi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng 2</p> <p>Gii thiu v cng ngh ASIC ASIC (Application Specific Intergrated Circuit): Mch tch hp ng dng chuyn bit. ASIC c xy dng bng vic kt ni cc khi mch c sn c xy dng theo cc phng php mi. sn xut ASIC thun tin v d dng hn ASIC l mt mch tch hp c sn xut cho mt ng dng c trng v thng c kch thc tng i nh ng dng: rng khp trong cc thit b iu khin t ng iu khin cc chc nng ca cc phng tin truyn thng, xe c, cc h thng x l, dy chuyn cng nghip</p> <p>Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng</p> <p>3</p> <p>S lc qu trnh pht trin ca mch tch hp IC Mch tch hp vi mt rt cao (VLSI) Trong nhng nm 1980 cc k s bt u khai thc nhng u im thit k IC theo nhu cu ca mnh hoc thit k cc h thng, cc ng dng c bit hn so vi cc IC chun. n cui nhng nm 1980, cc ngn ng m t phn cng nh VHDL v Verilog ra i, cc b m phng tc cao cho php cc mu thit k c hiu lc nhanh chng. Cc cng c tng hp t ng phin dch hot ng ca m hnh HDL thnh mt m hnh cu trc logic.</p> <p>Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng</p> <p>4</p> <p>Phn loi ASICLogic Standard LogicProgrammable Logic Devices</p> <p>ASIC Gate Arrays Cell-Based ICs</p> <p>(PLDs)</p> <p>Full Custom ICs</p> <p>SPLDs (PALs)</p> <p>CPLDs</p> <p>FPGAs</p> <p>ASIC c ch hon ton ( Full- custom ASIC) ASIC da trn cc t bo chun ( Standard- Cell- Based ASIC) ASIC da trn mng cng logic (Gate- Array-Based ASIC) Cc vi mch lp trnh c ( PLD: Programmable Logic Device) SPLD: Simple Programmable Logic Device CPLD (Complex Programmable LogicDevices) Mng cng logic c th lp trnh c theo trng/min (FPGA: Field Programmable Gate Array)</p> <p>Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng</p> <p>5</p> <p>ASIC c ch hon ton ( Full- custom ASIC) Mt phn hoc ton b cc logic cell v cc mch hoc nn (layout) c thit k ring bit cho tng ASIC. Khng s dng c th vin t bo c sn cho tt c hoc mt phn thit k. Gi thnh cao 8 tun ch to (khng k thi gian thit k)</p> <p>Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng</p> <p>6</p> <p>ASIC da trn cc t bo chun ( Standard- Cell- Based ASIC) Cn gi l CBIC (Cell-based ASIC ) s dng cc t bo logic thit k sn (cng AND, OR, MUX, FF) c gi l cc t bo chun. C th s dng kt hp t bo chun vi cc t bo ln c thit k sn (nh b VK, VXL) gi l siu t bo (megacell). Ngi thit k ch cn nh ngha v tr ca t bo chun v kt ni (interconnect) trong mt CBIC. Tt c cc lp mt n (mask layer) c ty bin v c thit k duy nht cho tng khch hng. u im: tit kim thi gian, tin bc v gim ri ro do s dng th vin t bo chun thit k sn v kim tra trc. Nhc im: Thi gian thit k hay chi ph mua th vin cell Thi gian ch to cc mask layer</p> <p>Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng</p> <p>7</p> <p>ASIC da trn cc t bo chun ( Standard- Cell- Based ASIC) Mt ASIC da trn t bo chun</p> <p> CBIC cu to t 1 vng t bo chun (flexible block) v 4 khi c nh Khi linh hot cha cc hng ca cc t bo chun. Cc vung nh quang ra CBIC c ni n chn linh kin T bo chun c thit k gn ging vi cc vin gch xy tng.8</p> <p>Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng</p> <p>ASIC da trn mng cng logic (Gate- Array-Based ASIC) L ASIC c c sn bng mng cc cng hoc cc cell ging ht nhau nhng cha c kt ni vi nhau. Cc cell ny c t ti cc v tr xc nh trc. Ch vi lp kim loi trn cng, phn nh ngha kt ni gia cc cell l c nh ngha bi ngi thit k nh mt n ty bin mng cng mt n (MGA) Mng cng (GA) c to t cc basic cell, mi cell gm mt s trasistor v in tr ty thuc vo mi hng. Ngi thit k s dng mt th vin cell (cc gate, thanh ghi) v mt th vin macro (cc tnh nng phc tp hn) cng vi phn mm ca hng to ra mt n ty bin. Trong GA, do cc cell c t ti cc v tr c nh nn mt s cell s khng c dng n</p> <p>Gate Array Cells.</p> <p>Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng</p> <p>9</p> <p>Cc vi mch lp trnh c ( PLD: Programmable Logic Device) PLD l cc IC chun. Tuy nhin PLD c th c cu hnh hay lp trnh to nn 1 b phn ty bin cho cc ng dng ring bit nn chng cng thuc h ASIC. c im chnh ca PLD Logic cell v mask layer khng c ty bin Thit k nhanh, gi thnh r Mt khi n l ca kt ni c th lp trnh Mt ma trn ca siu t bo logic thng gm mng logic c th lp trnh c theo sau bi FF hoc Latch.10</p> <p>Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng</p> <p>Cc vi mch lp trnh c ( PLD: Programmable Logic Device) Programmable Logic Device (PLD, PLA, PAL, ...) AND-OR combinatorial logic, plus FF Cho php thc hin cc mch logic tc cao. Tuy nhin cu trc n gin ca n ch cho php hin thc cc mch logic nh. PLA (Program. Logic Array): Khi AND kh trnh, khi OR c nh PLA :Khi AND v OR u kh trnh. PLA c th l mask- programmable hay field- programmable. Complex PLD (CPLD) Gm vi khi PLD Ma trn cc kt ni kh trnh FPGA: mng logic c th lp trnh Chip c c sn vi cc khi logic v cc kt ni Cc khi logic v kt ni kh trnh (c th xa v lp trnh nhiu ln). Khng cn ch to Gi thnh thp, ph hp vi thit k c phc tp trung bnh (</p>