Chuong 2 - Tong Quan Ve Vi Xu Ly

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CHNG 2TNG QUAN V H VI X L

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Mc lc2.1. Gii thiu chung 2.2. Cu trc mt h Vi x l in hnh 2.3. Chu k trong Vi x l 2.4. Tp lnh ca Vi x l 2.5. Ghp ni b nh

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2.1. Gii thiu chung2.1.1. nh ngha Vi x l L mch bn dn tch hp trn mt chip (IC) c nhim v thc hin cc cng vic x l tn hiu hoc iu khin cc thnh phn trong h thng Vi x l thc hin cng vic ca n theo chng trnh, thut ton do ngi dng t ra K hiu: P hoc uP

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2.1. Gii thiu chung Phn loi Vi x l

Vi x lLoi a nng:Phc v cho nhiu mc ch khc nhau V d: 8080, 8085 ca Intel 6800, 6802 ca Motorola

Loi chuyn dng:Phc v mt mc ch c th V d: cc IC trong chi ca tr em

Hoc phn loi theo s lng bit: Vi x l 4bit, 8bit, 16bit, 32 bit v by gi l 64bit. Chip ca Intel dng nhiu trong my tnh cn ca Motorola dng nhiu trong vin thng4

2.1. Gii thiu chung Lch s ra i v pht trin ca Vi x l2005 Power PC (IBM) 64bit 1993 1999 32 bit AT&T: BELLMAC-32A 1985 1976 1971

Intel: Multi Core 1990 Intel: Pentium, Xeon, Celeron

1960 Intel: 4004, 8008, 8080 Fairchild Semiconductor: Chip bn dn u tin Thng mi ha chip bn dn

1982 Motorola: 680xx ARM I Zilog: Z-80 TI: VXL 16bit

Tng mt , My tnh trn chip

VLSI v 32 bit

32bit nhng ch 64bit

K nguyn a li

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2.1. Gii thiu chung2.1.2. H Vi x l nh ngha: L h thng s lm vic theo chng trnh c lu gi trong b nh, x l d liu bng vi x l v a ra cc quyt nh lin lc vi th gii bn ngoi thng qua cc cng vo ra Mt h Vi x l lun bao gm 2 thnh phn: Phn cng v phn mm

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2.1. Gii thiu chung2.1.3. Cc thnh phn trong h Vi x l

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2.1. Gii thiu chung2.1.4. Cc kin trc thng dng ca Vi x l Kin trc Von Neumann

Ch c mt b nh chung cho d liu v chng trnh c d liu v c lnh khng din ra ng thi

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2.1. Gii thiu chung Kin trc Von Newmann

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2.1. Gii thiu chung Kin trc Harvard

C cc bus c lp cho b nh chng trnh v d liu c d liu v c chng trnh din ra ng thi

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2.1. Gii thiu chung Kin trc Harvard

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2.1. Gii thiu chung Kin trc SHARC Super Harvard Architecture

Thm vo mt s c trng ci thin bng thng d liu

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2.1. Gii thiu chung Kin trc DSP Digital Signal Processing

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2.2. Cu trc ca mt h VXL in hnh2.2.1. Cu trc chung ca mt h VXL in hnh

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2.2. Cu trc ca mt h VXL in hnh Cu trc rt gnAddress Bus Data bus

uP

M

I

OControl bus

uP: Vi x l M: B nh (Memory) I: Cng vo/Thit b vo d liu (Input) O: Cng ra/Thit b xut d liu (Output)15

2.2. Cu trc ca mt h VXL in hnh2.2.2. Cc thnh phn c bn trong h VXL 1. H thng BusKhi nim

A

BBus

C

D

Kt ni kiu kinh in

Kt ni kiu Bus16

2.2. Cu trc ca mt h VXL in hnh Bus l nt dng chung ca c h thng, dng truyn d liu gia cc thnh phn vi nhau Bus c th nm trong hoc nm ngoi Vi x l Truyn thng song song: Bus l di (tape) dy dn, mi dy truyn 1 bit. Truyn thng ni tip: Bus c th l cp ng trc, xon i, quang

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2.2. Cu trc ca mt h VXL in hnhT chc v qun l Bus Bus s dng phn t 3 trng thi cch ly cc phn t trong h thng Cc phn t trong h thng Bus c qun l bng a ch. Mi thnh vin trong h u c xc nh 1 a ch duy nht Qun l a ch bng phn cng (mi u dy, I/O c 1 a ch xc nh) hoc bng phn mm (a ch IP)

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2.2. Cu trc ca mt h VXL in hnh Truy cp Bus: Phng php ngu nhin: thi im truy cp bus ca cc phn t l ngu nhin. Dng trong qung b Tc chm Qun l s lng phn t ln Cn gii quyt vn xung t

Phng php tin nh: xc nh trc quy lut, thi gian truy nhp Tc cao S phn t t

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2.2. Cu trc ca mt h VXL in hnhu nhc im u im: Tit kim, n gin ha h thng Lm h c tnh m. C th thm hoc bt phn t d dng

Nhc im: Tc b hn ch do Bus l ng truyn chung

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2.2. Cu trc ca mt h VXL in hnh2. T chc cng vo ra Thit b c bn IC 8282 Tch hp mch 3 trng thi v cht d liuD0

D0 D7: 8 ng d liu voD STB OE Q0

Q0 Q7: 8 ng d liu ra STB: cht tn hiu STB = 1: cho php a d liu ra STB = 1->0: cht d liu u ra

D7

D STB OE

Q7

/OE: Cho php xut tn hiu

STB

OE

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2.2. Cu trc ca mt h VXL in hnhT chc cng voD0..D7 +5V STB 8282 OE

- Ax: a ch ca thit b (Tn hiu sau gii m a ch) - IO/M: Tn hiu chn thit b: IO/M = 1 chn cng vo ra IO/M = 0 chn b nh - /RD: Lnh ch thao tc c thit b

Data bus

Address bus

Ax

IO/M RD Control bus

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2.2. Cu trc ca mt h VXL in hnh

Address Bus

Ax = 1

IO/M = 1 Control Bus RD = 0

Data Bus

Data t bn ngoi

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2.2. Cu trc ca mt h VXL in hnh T chc cng raQ0..Q7

OE 8282 STB

Data bus

Address bus

Ax

IO/M WR Control bus24

2.2. Cu trc ca mt h VXL in hnh

Address Bus

Ax = 1

IO/M = 1 Control Bus WR = 0

Data Bus

Data a ra ngoii

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2.2. Cu trc ca mt h VXL in hnh3. B nh nh ngha: L thit b dng lu tr thng tin gm chng trnh v d liu Phn loi: B nh chnh: l b nh hot ng, yu cu tc cao. Ch to di dng b nh bn dn. VD: RAM B nh ph: yu cu cao v dung lng lu tr v thi gian lu tr. VD: ROM, HDD

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2.2. Cu trc ca mt h VXL in hnh T chc ca b nh: B nh c to thnh t cc nh sp xp cnh nhau v mt logic. Cc tham s ca nh gm: V tr (logic) ca nh: l a ch ca nh, do bus a ch truyn i trong h Ni dung ca nh: l d liu cha trong nh, do bus d liu truyn i trong h. Thng thng, mi nh c ln l 8bit (1byte) Qun l b nh bng phng php a ch ha cc nh27

2.2. Cu trc ca mt h VXL in hnh Cc phng php a ch ha nh Phng php a ch tuyt i: a ch ca mt nh chnh l khong cch ca n so vi a ch gc a ch gc thng c xc nh l 0 ng dng cho cc loi b nh dung lng nh

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1110

15 nh 3 2 1 0 11 10 1 0

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2.2. Cu trc ca mt h VXL in hnh Phng php a ch on Chia ton b b nh thnh nhiu vng (segment), mi vng c mt a ch xc inh. a ch ca mt nh trong b nh c xc nh bi: a ch ca segment cha nh a ch offset ca nh trong segment

a ch offset

Segment n

Segment 1

a ch segment

Segment 029

2.2. Cu trc ca mt h VXL in hnh Phng php a ch on (tip) Cc thit b lu tr a ch nh c kch thc nh V d: 8085A a ch ha nh bng 16bit -> Dng 2 thanh ghi 8bit, 1 thanh ghi cha a ch segment, 1 cha a ch offset

Qun l c b nh c dung lng ln

Khng gian nh: ton b a ch c th a ch ha c ca b nh Nu bus a ch c n bit th khng gian nh l 2n a ch

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2.2. Cu trc ca mt h VXL in hnh Bn b nh: cho thy b nh hay cc thit b c kt ni vi bus a ch c t u trong khng gian nh V d:

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2.2. Cu trc ca mt h VXL in hnh4. Vi x l - 8085 Mt s c tnh c bn: B x l 8 bit tc 3 6MHz 4 u vo ngt C cc cng vo ra ni tip C kh nng tnh ton s hc thp phn, nh phn v du phy ng Chu k lnh 0.8s a ch ha trc tip cho 64KB b nh .32

2.2. Cu trc ca mt h VXL in hnh Bus a ch: AD0 AD7 v A8 A15 Bus d liu: AD0 AD7 Bus iu khin: IO/M, RD, WR ALE: Cho php cht a ch SID, SOD: vo/ra d liu ni tip S0, S1: trng thi chu k mySID AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 X1 X2 HOLD INTR READY RST 5.5 RST 6.5 RST 7.5 RSTIN TRAP 8085VCC

S chn linh kin

5 12 13 14 15 16 17 18 19 1 2 39 10 35 9 8 7 36 6

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U5

SOD A8 A9 A10 A11 A12 A13 A14 A15 CLKOUT ALE HLDA INTA IO/M RD RSTOUT S0 S1 WR

4 21 22 23 24 25 26 27 28 37 30 38 11 34 32 3 29 33 31

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GND

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2.2. Cu trc ca mt h VXL in hnh Phi hp cc tn hiu iu khin /RD IO/(/M)

MEMR: cho php c t b nh MEMW: cho php ghi b nh I/OR: cho php c t cng vo I/OW: cho php ghi ra cng ra4 2 5 /MEMR IO/(/M) 5 /WR 4 2 /MEMW

/WR /RD 4 2 5 IO/(/M) IO/(/M) 1 2 1 2 /I/OR

4 2 5 /I/OW

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2.2. Cu trc ca mt h VXL in hnh Biu thi gian lm vic trong 8085

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2.2. Cu trc ca mt h VXL in hnh S cu trc Vi x l 8085

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2.2. Cu trc ca mt h VXL in hnh Cc thnh phn in hnh: n v iu khin (Control Unit): iu khin v ng b qu trnh trao i v bin i s liu trong h Vi x l. n v logic s hc (Arithmetic Logic Unit ALU) thc hin cc php ton H thng thanh ghi: lu gi d liu tm thi phc v cho tnh ton. 8085 c 7 thanh ghi mc ch chung 8 bit B, C, D, E, H, L v c th ghp thnh 3 thanh ghi 16 bit.

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2.2. Cu trc ca mt h VXL in hnh Cc thnh phn in hnh: Thanh cha (Accumulator A) l mt thnh phn ca ALU. Cha d liu 8 bit H thng c (Flag F) C khng Zero (Z) C nh Carry (C) C du Sign (S) C chn l Parity (P) C nh ph Auxiliary Carry (AC)

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2.2. Cu trc ca mt h VXL in hnh Cc thnh phn in hnh: B m chng trnh (Program Counter PC): 16 bit, l con tr b nh. Dng lp trnh t thc hin lnh trong Vi x l Con tr ngn xp (Stack Pointer SP): 16 bit, cng l con tr b nh, tr n vng nh ngn xp (stack) Thanh ghi lnh v gii m lnh (IR, ID): lu gi tm thi lnh hin thi ca chng trnh (IR), ID s gii m lnh thnh cc vi lnh

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2.2. Cu trc ca mt h VXL in hnh Thanh ghi a ch b nh: lu gi a ch, nhn v t PC, ca cu lnh tip theo B pht xung iu khin (Control Generator) to ra cc xung trong uP thc hin cc lnh c gii m B chn thanh ghi (Register Selector) iu khin vic la chn s dng cc thanh ghi trong h thng thanh ghi ca uP

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2.2. Cu trc ca mt h VXL in hnh Qu trnh thc hin lnh a ch lnh u tin: n Sau Reset, IP = 0 Khi thc hin, IP = n a ch trong IP ch ra v tr cu lnh trong chng trnh

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2.2. Cu trc ca mt h VXL in hnh Qu trnh thc hin lnh (tip)((IP)) -> uP

ID gii m lnh

IP ++

Lnh c thc hin

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2.3. Chu k trong Vi x l1. Chu k lnh (Instruction Cycle) Khong thi gian Vi x l thc hin mt lnh t b nh chng trnh. 2. Chu k my (Machine Cycle) S bc m vi x l thc hin ng vi mt lnh nhn c. Thng gm 4 bc: c lnh, dch lnh, thc hin lnh v lu gi kt qu Bng mt s nguyn ln xung ng h

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2.4. Tp lnh ca Vi x l 4 nhm lnh ch yu: Nhm lnh di chuyn d liu VD: MOV A, B

Nhm lnh tnh ton logic VD: ANL A, R0

Nhm lnh ton hc VD: ADD A, R1

Nhm lnh nhy v r nhnh VD: JNB TF0, LOOP VD: ACALL LOOP

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2.4. Tp lnh ca Vi x l Ngy nay, tp lnh ca VXL ngy cng phong ph, thi gian thc hin lnh ngy cng nhanh Do s pht trin v cng ngh ch to Do mc tch hp cc thit b ngoi vi Do s a dng ca cc sn phm Do s a dng ca cc hng sn xut .

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2.5. Ghp ni b nh2.5.1. Mt s chip nh thng dng 1. ROM Thit k bi cng ngh NMOS, CMOS Dung lng thng 2Kbyte 64Kbyte D liu lu tr dng ma trn Khng b nh hng bi vic mt in 2716, 2732, .., 27256

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2.5. Ghp ni b nh V d ROM 2716

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2.5. Ghp ni b nh2. RAM Static RAM Mi bt d liu c lu tr bi cp flip-flop Cu trc n gin Ghi v xa tn hiu bng in D liu mt i khi mt in Tiu th nng lng ln khi c in Kch thc ln khi dung lng ln 6216, 6232, ..62256

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2.5. Ghp ni b nh Dynamic RAM D liu ghi bng t D liu phi refresh tng 2ms -> phi c b iu khin refresh Dung lng ln Cu trc ma trn t tn hao in

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2.5. Ghp ni b nh V d: RAM 62256

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2.5. Ghp ni b nh2.5.2. Ghp ni nhiu b nh Ghp ni cc chip nh 2Kx8bit to ra b nh 4Kx8bit Mt s ch : S lng bit a ch phi ph hp Thng nht tn hiu iu khin B nh 2Kx8bit c 11 bit a ch trong khi 4Kx8bit c 12bit a ch

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2.5. Ghp ni b nhA0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 U3 A11 2 1 18 8 7 6 5 4 3 2 1 23 22 19 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 D1 D2 D3 D4 D5 D6 D7 D8 OE WE 9 10 11 13 14 15 16 17 20 21 U1 2016 D0 D1 D2 D3 D4 D5 D6 D7Data[0..7]

A[0..11]

/RD /WR

CE

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10

NOT

8 7 6 5 4 3 2 1 23 22 19

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10

D1 D2 D3 D4 D5 D6 D7 D8 OE WE

9 10 11 13 14 15 16 17 20 21 U2 2016

D0 D1 D2 D3 D4 D5 D6 D7

/RD /WR

A11

18

CE

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2.5. Ghp ni b nh2.5.3. Thit lp b nh ti a ch xc nh

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