Comparison of various TSV technology ELEC 5070 Term paper SONG Wenjie

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Comparison of various TSV technologyELEC 5070 Term paperSONG WenjieOutline What is Through Silicon Via(TSV) Advantages of TSV Various TSV TechnologyOutline What is Through Silicon Via(TSV) Advantages of TSV Various TSV Technology What is Through Silicon Via(TSV)

High integration technology Small, high speed, multi-functional devicesThis miniaturization is technologically (limited by)the leak current generates heat & signal delay in circuit (caused by) wiring3D packaging technology are expected to make a breakthrough in such miniaturization on 2D surface (enable)high density integration by stacking LSI chips with smaller footprint save the space that would be necessary for bonding wires improve packaging densityOutline What is Through Silicon Via(TSV) Advantages of TSV Various TSV TechnologyAdvantages of TSV1) Small size and high densityCan be used for the perpendicular construction of LSIs in a 3D space, and require a footprint at a fraction of that of a conventional LSICan potentially be used effectively for stacking processor cores in a CPU composed of multi cores to realize a highly parallel processor LSI2) High speed signal propagation and processingReduce the total wiring lengthHigher speeds in signal propagation and a reduction of signal delaysIncrease the design flexibility3) Low power consumptionElectrical resistance causes heating, enables the elimination of such heatingReducing the number of repeaters(save power)4) Many input-output terminalsWire bondings are located at the edges of an LSI chip, whereas , TSV place input-output terminals in arbitrary positions in an LSI chip

Outline What is Through Silicon Via(TSV) Advantages of TSV Various TSV TechnologyTSV FabricationTSV AssemblyDesign, Test, Characterization & ReliabilityPost-TSV ProcessVarious TSV TechnologyTSV enabling technologiesVia first/lastHigh AR viaThin wafer handlingVia exposureRDL(Re-distribution layer) - BumpStackingC2C,C2W bondingFine gap underfillVarious TSV TechnologyTSV FabricationProcess Flow:

Via first/lastHigh AR viaThin wafer handlingVarious TSV TechnologyTSV Fabrication

Vertical via - is suitable for finer pitch ( 150 um). It is used for power amplifier (PA) backside ground applications and CMOS TSV image sensors.Via first/lastHigh AR viaThin wafer handlingVarious TSV TechnologyTSV FabricationVia-First ProcessThe dimensions are typically smaller (520 m wide), with aspect ratios of 3:1 to 10:1.

Via-Last ProcessThe dimensions are wider (2050 m), with aspect ratios of 3:1 to 15:1.Via first/lastHigh AR viaThin wafer handlingVia-First : interfere with device layerVia-Last : interfere with both device and metal layers11Various TSV TechnologyTSV FabricationTechniques for forming high aspect ratio deep silicon via structures:

Bosch etch processcryogenic etch processlaser drillingpowder blast micromachiningVia first/lastHigh AR viaThin wafer handlingVarious TSV TechnologyTSV FabricationBosch etch process:Via first/lastHigh AR viaThin wafer handling

C4F8 passivationFluorine radicals(in SF6 )removing passivation layer of the base of the trenchSF6 etch the exposed silicon at bottomPro: Very high aspect-ratio (>60:1) sub-micronCon: A characteristic sidewall ripple of 100200 nmVarious TSV TechnologyTSV FabricationCryogenic etch process:Via first/lastHigh AR viaThin wafer handlingPro: low sidewall roughness (a few nanometers)Con: fast etch rate (passivation and etching proceed concurrently)Perform two steps simultaneously using SF6 and O2 gasesSiOXFY on the sidewalls (@T-100 C) passivation

Various TSV TechnologyTSV FabricationLaser drilling process: Via first/lastHigh AR viaThin wafer handling

Pro: significant low cost due to lithography freeCon: heat from lasers lead to low reliability and stress gradientVarious TSV TechnologyTSV FabricationPowder blast micromachining:Via first/lastHigh AR viaThin wafer handlingA particle jet is directed toward the target materialCyclone ventilate particles 80-200 m/s

Various TSV TechnologyTSV FabricationThin (~50m) wafer handling:

UV curable epoxy/glass bonding Using glass wafer as supporting, dispensed UV curable epoxy to bonding and debondingPolymer adhesive Using high temperature polymer materials to meet process temperature needs and debond from support wafers @ 200~250C Electrostatic bonding Using electrostatic bonding, wafer can be temporary attached to electrostatic chuck for several hours.Via first/lastHigh AR viaThin wafer handlingVarious TSV TechnologyTSV FabricationThe main challenges :smooth via sidewallsuniform deposition of dielectric isolation layer over the via sidewallcontinuity of copper diffusion barrier and copper seed metallization void-free copper electroplating.

Via first/lastHigh AR viaThin wafer handlingThanks for your attention