Consistent Resume - Chiappetta

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<ul><li><p>Erasmo J. D. Chiappetta Filho M.Sc. Analog/Mixed-Signal IC Designer Eldorado Research Institute</p><p>email: erasmocf@gmail.comskype: erasmo.chiappetta.filhophone: +55 (19) 99761-2553</p><p>Summary Experience on analog and mixed signal design, layout and silicon validation. Experience with the whole set of Cadence tools for analog and mixed signal design. Worked in 8 Tape-outs: Three times in 65nm (in two different foundries), one tape-out in 0.35um, and </p><p>four tape-outs in 180nm (three of them in commercial foundry and one in a medical certified foundry). Experience on silicon validation and laboratory automation. Experience as team leader and enthusiastic of team building and collaboration. A total of 8 publications, including 4 in international conferences and one in an international journal. Able to work in Europe due to dual citizenship (Brazilian / Italian).</p><p>SkillsEDA Softwares:</p><p> Cadence Virtuoso tools set (6+ years). Calibre - nmDRC, nmLVS, nmPEX (5+ year). ICstudio, IC Station, Design Architect-IC (1 year). HSPICE, AvanWaves (2 years).</p><p>Programming Languages: Python, for scientific computing and laboratory automation. Perl, Tcl and Bash. Skill</p><p>HDL Languages: Verilog Verilog-A/AMS</p><p>Other: MATLAB, Scilab Labview CST (finite elements solver)</p><p>Career SummaryApr 2014 Present Analog/Mixed Signal IC Design Team Leader, Eldorado Research Institute.Jun 2012 Jun 2015 Master Degree at State University of Campinas (UNICAMP).Sep 2009 Apr 2014 Analog/Mixed Signal IC Designer, Eldorado Research Institute.Aug 2007 Jan 2009 Junior Researcher, Nangate Research Lab.</p><p>mailto:erasmocf@gmail.com</p></li><li><p>ExperienceEldorado Research Institute</p><p> Analog IC Design Team Leader for Implantable Pacemaker in 180nm CMOS. Team Leader and responsible for the analog section of the SoC. Lead engineer of the post-silicon analog validation team. Front-End Architecture development. Interaction with all knowledge fields involved in the project. Responsible for Top-Level Floorplan and Layout. Managed the designers for tape-out of test circuits (8 weeks from design to GDSII, 6 dies in total). Close work with Modeling Team (Matlab and Verilog-A). Close Interaction with team from abroad (California and Sydney). Attended to Fernando Silveira's course on various pacemaker design subjects.</p><p> Mixed Signal IC designer of EPCglobal Gen2 RFID Tag in 180nm CMOS. Integration of chip top level (analog + digital blocks). Interaction with Verification team, reviewing the Verilog simplified models for the analog blocks. Leaded the RF Team for improvements and bug fixes of the RFID system. Power consumption minimization by detailed analysis of the system to find and fix power sinks. Responsible for pad ring improvements. Logic modification and layout. Redesigned RFID modulator (from schematic to layout). Use of Python to model equations and plot simulation results. Main responsible for analog measurements in the lab. Close Interaction with team from abroad (California).</p><p> Mixed Signal IC designer of High-speed (6GHz), Low-area, Integer-N PLL in 65nm CMOS. Schematics porting and optimization of various blocks. Layout of customized standard cells, aiming high-speed. Layout of top level (120m x 110m). Abstracts generation. Parasitic extraction and simulation of all blocks. Frequent interaction with team from abroad (California and Sydney).</p><p> Mixed Signal IC designer of 16bit, 2.4GHz oversampling DAC in 65nm CMOS. Short design-to-silicon time (one month). PDK installation. Optimized the analog DAC for INL of 0.25LSB for 16 bits. Optimized digital critical path for speed (pipe line). Layout of the analog DAC and the full custom digital circuit. Top level layout (87.7m x 145m). Behavioral modeling using Python Script. Daily interaction with Sydney team.</p><p> Analog IC designer of metal fix tape-out of EPCglobal Gen2 RFID Tag in 180nm CMOS. Responsable for re-wire pads internal circuitry to increase its speed when working at 1V Vdd. Mapped all circuitry from pads to find the speed critical paths. Re-wired the transistors with only M1, M2, M3, M4, VIA2 and VIA3 (no VIA1 or contacts available).</p><p> Analog IC designer and test engineer of 915MHz EPCglobal Gen2 RFID Tag in 180nm CMOS. Full chip power consumption simulations. Pad ring layout. Automation of silicon test-bench to test the analog portion.</p></li><li><p> Analog IC designer and test engineer of 16bit, 2.56MHz Sigma-Delta ADC in 180nm CMOS. Integrators design and layout. Switches design and layout. Assisted top level simulation. Chip integration layout (900m x 800m). Responsable for the silicon test and laboratory automation, including temperature sweep. RTL coding to use an FPGA to acquire ADC output signal.</p><p>Nangate Research Lab. International R&amp;D environment (Brazil, Russia, USA, Denmark). Junior Researcher</p><p> Automation of standard cell library characterization. Liberty files generation. Research on estimation of delay and power consumption of logic cells to support a full custom </p><p>design.</p><p>Education2015 Master of Science. (Microelectronic Sensors). State University of Campinas (UNICAMP).2014 Power minimization in High-speed Analog ICs. Prof. Willy Sansen (KU Leuven).2014 Design Methodology for Medical Devices. Prof. Fernando Silveira (Universidad de La Republica, Uruguay).2011 Preparatory for the PMP Exam of the PMI Project Management Processes. Gapcon.2011 Project Management. Dextra Sistemas.2009 Cadence 6 months Course in Analog/Mixed Signal Design. Brazilian Ministry of Science and Technology.2009 Bachelor of Engineering (Electrical Engineering) Federal University of Rio Grande do Sul (UFRGS). </p><p>Publications and Patents</p><p> M. Franco, J. Giza, E. Chiappetta, S. Rueda, H. Luis, J. Bertuzzo, J. Koeppe, T. Robins, J. Jenkins, T.Hamilton, "Electronically Programmable Test Points for On-Chip Analog/Digital Measurements", 2013IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 May 2013.</p><p> E. Chiappetta, S. Rueda, M. Franco, F. Souza, J. Bertuzzo, J. Jenkins, "Fully Automated, Low Cost,Bench-Testing Solution for Analog/Mixed-Signal Integrated Circuits", Workshop on Circuits and SystemDesign (WCAS), Curitiba, Brazil, 3-6 September 2013.</p><p> Erasmo J. D. Chiappetta Filho , Luiz E. Bento Ribeiro , F. Fruett, "Full Design of an ElectrochemicalImpedance Spectroscopy Sensor", Workshop on Circuits and System Design (WCAS), Curitiba, Brazil,3-6 September 2013.</p><p> Butzen, Paulo F. ; da Rosa Jr, Leomar S. ; CHIAPPETTA FILHO, E. J. D. ; Reis, Andr I. ; Ribas, RenatoP. . Standby power consumption estimation by interacting leakage current mechanisms in nanoscaledCMOS digital circuits. Microelectronics (ISSN 0959-8324 Microelectronics Journal), v. 41, p. 247-255,2010. </p><p> BUTZEN, P. F., ROSA JUNIOR, L. S., CHIAPPETTA FILHO, E. J. D., MOURA, D., REIS, A. I., RIBAS, R.P., Simple and accurate method for fast static current estimation in CMOS complex gates withinteraction of leakage mechanisms. In: Great Lakes Symposium on VLSI (GLSVLSI), 2008, Orlando. </p><p> BUTZEN, P. F., ROSA JUNIOR, L. S., CHIAPPETTA FILHO, E. J. D., MOURA, D., REIS, A. I., RIBAS, R.P., Subthreshold and Gate Leakage Estimation in Complex Gates In: 17th ACM/IEEE InternationalWorkshop on Logic and Synthesis (IWLS), 2008, Lake Tahoe. </p></li><li><p> CHIAPPETTA FILHO, E. J. D., BUTZEN, P. F., ROSA JUNIOR, L. S., REIS, A. I., RIBAS, R. P., ASIMPLE MODEL TO ESTIMATE INTRINSIC POWER CONSUMPTION IN CMOS LOGIC GATES In: VIIIMicroelectronics Students Forum, 2008, Gramado. </p><p> BUTZEN, P. F., ROSA JUNIOR, L. S., CHIAPPETTA FILHO, E. J. D., MOURA, D., REIS, A. I., RIBAS, R.P. Accurate Method for Subthreshold and Gate Leakage Current Estimation in CMOS Complex Gates In:XXIII South Symposium on Microelectronics (SIM), 2008, Bento Gonalves. </p></li><li><p>Erasmo J. D. Chiappetta FilhoSummarySkillsCareer SummaryExperienceEducationPublications and Patents</p></li></ul>