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: : , . Tanenbaum, Vrije Universiteit, Amsterdam. Computer Architecture and Engineering, K. Asanovic, CS1/2-52, University of Berkeley. , . , . , . , , . , . : .. , , .Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

, , , , Pentium 4

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

;

. , .19/10/08CS252-s06, Lec 01-intro

3

, ,

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

(1) assembly

( )

. () .Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

(2)

Assembler, Linker Firmware . . . I/O

Assembly

/

6

cslab@ntua 2007-2008

Assembly Assembly, 0000 1010 1100 0101

temp=v[k]; v[k]=v[k+1]; v[k+1]=temp;

load$15,0($2) load$16,4($2) store$16,0($2) store$15,4($2)1001 1111 0110 1000 1100 0101 1010 0000 0110 1000 1111 1001 1010 0000 0101 1100 1111 1001 1000 0110 0101 1100 0000 1010 1000 0110 1001 1111

ISA

, Control Signal Specificationcslab@ntua 2007-2008

ALUOP[0:3] > > 2. Bottom Up > > > * (Hardware/Software Co-design) * (Backward Compatibility)

14cslab@ntua 2007-2008

, (). = , , , , , = , , = , () , ..15cslab@ntua 2007-2008

(1)Time = I x CPI x Clock Cycle Time- I: Instrumentation ( , ) - CPI: Cycles Per Instruction (, o) - Clock Cycle Time: ( ) , CPI Clock Cycle Time ( ) Clock Cycles = CPIi x i i: (CPIi) (i) .cslab@ntua 2007-2008

16

(2)FLOPs: Floating Point Operations per Second MIPs: Million Instructions per Second MIPs = / 106 /CPI X 106 1 ( ) : 1GHz, 1 GFLOP 1 , 1000MIPs

4 x freq FLOPS < {single Core 2 @ 2.93GHz} < 8 x freq FLOPs , FPADD, FPMUL, FPDIV ( ). 12 GFLOPs/cpu17cslab@ntua 2007-2008

(3)SPEC Benchmark () www.spec.org i execution ratio (ER) ERi=( 300 MHz UltraSun 5_10 / )* 100 Execution Ratios n ______ SpecRatio = (ERi) i=1,2,..,n - SPEC CPU2006: 12 integer 17 floating point - SPECThroughput, SPECJava... 18cslab@ntua 2007-2008

TOP 500, 13/06/08

19cslab@ntua 2007-2008

()* Patterson & Hennessy, Computer Organization and Design , . '' .. MIPS. .

* Bryant, O'Hallaron, Computer Systems: A Programmer's Perspective . '' .. 32. . .

* Tanenbaum, Structured Computer Organization , , . . .. . .

*Hamacher et.al., Computer Organization *Stallings, Computer Organization and Architecture. . .20cslab@ntua 2007-2008

()* Compus, httlp://compus.uom.gr , , , .

* PdP Lab, http://www.it.uom.gr/teaching , , . Compus.

* Wikipedia computer architecture . * Google..

21cslab@ntua 2007-2008

1-2 3-5 6-8 9 10 11-12 13 , , .., (ssembly) 1,2,3 4 5 6 7 8 -

22cslab@ntua 2007-2008

. (. , ). ' : ', 4 5 - 6,7 8. 1,2 3, . , . MIC-1. Intel gcc, gdb / ddd (Linux). / (+20%).23cslab@ntua 2007-2008

, , , , Pentium 4

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

: , , (1945) (1950) (1960) (1970) (1985) : , , (2000) (VLSI)

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

(1)

.Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

(2)

.Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

(1642 1945) (1945 1955) -Transistors (1955 1965) (1965 1980) -VLSI (1980 ?)

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

19/10/08

EDSAC, University of Cambridge, UK, 1949CS252-s06, Lec 01-intro

29

Von Neumann. bit-level . .Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

PDP-8. (). -.Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

IBM 360: . . .Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

- ( Intel). ( PC) (). (Miscrosoft MSDOS) (3rd parties). VLSI: , . - . : - .Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0 Tanenbaum, Structured

Moore (1)

(K) (LSI, VLSI). Moore 60% transistors chip. bits.Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Moore (2): 2X 1.5 . ~1000X 10. : DRAM : > 2x 1.5 . ~1000X 10. bit: 25% . : : > 2X 1.5 . bit: 60% . 200X 10.35cslab@ntua 2007-2008

.. Sensor Nets TIFF (Uncompressed) decompressor QuickTime see this picture. are needed toand a Cameras Games QuickTime Set-top and a TIFF (Uncompressed) decompressor are needed to see this picture. boxes Media Players Laptops ServersQuickTime and a TIFF (Uncompressed) decompressor are needed to see this picture.QuickTime_ and a TIFF (Uncompressed) decompressor are needed to see this picture.

Smart phones Automobiles19/10/08

Routers

Robots

Supercomputers 36

CS252-s06, Lec 01-intro

, .Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

- Pentium 4 Intel (-32) - UltraSPARC III Sun Microsystems - 8051 chip Intel, - PS, - ARM, - PIC, ? : .Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

, , , , Pentium 4

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

(PC)

.Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

''

(, ) CPU I/OTanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

CPUAddress Content00..0 01100..0

MAR, MDR PC, IR

FF..F

0100..0

Memory

CPU

( ) CPU = , ALU, .Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

(Program Counter, PC) (Instruction Register, IR) (Memory Address Register, MAR) (Memory Data Register, MDR) (Accumulator, AC) , , C... (Stack Pointer, SP) Index, Base, Offset Registers (Status Register, SR)Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

- A. B. C. D. , () CPU E. () CPU F. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

(1)

...

( Java).Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

(2)

( Java).Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

: . . -ROM.

. ( ). . / ( ).

( -ROM )

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

T CPU

(1-address)

. - . ( ).

(0-address)

( ) (Push, Pop). , . JVM.

(0,1,2-address)

. ( ) . ( RISC, CISC)Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

AC

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

ACint x, y, z; x = y + z; load 0xA2 add 0xA4 store 0xA0 0100 1010 0010 0110 1010 0100 0101 1010 0000 Assembly // AC := AC + mem(0xA4)

IR := MDR(PC); PC := PC + len(instr); Decode (Opcode(IR); MAR := Operand(IR);AC := MDR(MAR);

=

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Stack

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Stackint x, y, z; x = y + z; load 0xA2 load 0xA4 add store 0xA0 push 0xA2 push 0xA4 pop 0xA0 Assembly // pop, pop, add, push

0100 1010 0010 0100 1010 0100 0110 0101 1010 000

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Regs

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Regsint x, y, z; x = y + z; `` load A, 0xA2 load B, 0xA4 add C, A, B store C, 0xA0 Assembly load A, 0xA2 add C, A, OxA4 store C, 0xA0 add C, 0xA2, 0xA4 store C, 0xA0 add 0xA0, 0xA2,0xA4

0100 0000 1010 0010 0100 0001 1010 0100 0110 0010 0000 0001 0101 0000 1010 0000

; , ;

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

T

(/ /) , , ( PC) ( ) /'o /

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

: Top 10 Intel X86 Instructions 1 2 3 4 5 6 7 8 9 10 load conditional branch compare store add and sub move register-register call return Total 22% 20% 16% 12% 8% 6% 5% 4% 1% 1% 96%57

: .cslab@ntua 2007-2008

RISC CISC (VAX). (200-300 ). - . Complex Instruction Set Computer (CISC) . . , ' . .. . - '' . Reduced Instruction Set Computer (RISC) .. . (MIPS, SPARC, PowerPC, ..) ? RISC (Pentium, ..) ? CISC RISC ( ..).Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

' ( ). CPU ( , ILP). ( ). , Load, Store . ( register file).

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

(Data Level Parallelism, DLP): , ALU, , (32/64 bits, GPU). (Instruction Level Parallelism, ILP): ( , ). (Task/Thread Level Parallelism, Multithreading): (). (Functional Parallelism): ( GPU, DMA, I/O ..) / (Multiprocessors, Multicomputers): .Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

(ILP) CPU, - . , PC A 1 C D E Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

2

3

4

5

6

7

8

9

10

(ILP) Pipelining (, )

() () .

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

(ILP) (Superscalar) (1)

( Pentium, ).

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

(ILP) (Superscalar) (2)

, (Pentim II).Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

(ILP) (Superscalar) (3)

1 C D1 D2 D3 D4 D5 E

2

3

4

5

6

7

8

9

10

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

96 bit.Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Bytes (1)

(a) Big endian (b) Little endian

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

Bytes (2)

(a) big endian. (b) little endian. (c) big endian little endian. (d) bytes (c).Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

(Cache) (1)

() cache CPU .

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

(Cache) (2)

() , cache (L1/2/3) , (, ).

. : : , . :

: , : .

Cache L1 > K L2 > L3 > . L1 < L2 < L3 < . L1 < L2 < L3 < . Cache < 1% : * Cache ( ). * Cache , . * Cache .

L1 Instruction/Data on chip L2 on chip package L3 on board

*

*Virtual memory

* /

( ) . ( *).Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

(1)

.Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

(2) (Data Bus): MDR,IR, AC (A, B, C, ...) (Address Bus): MAR, PC, SP, Index,, Base (Control Bus): ..

masters slaves .

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

(1)

.Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

(2)

.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

(1)

(a) . (b) .Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

(2)

.

Tanenbau...