eisagogi

  • Published on
    17-Oct-2014

  • View
    25

  • Download
    0

Embed Size (px)

Transcript

<p> : : , . Tanenbaum, Vrije Universiteit, Amsterdam. Computer Architecture and Engineering, K. Asanovic, CS1/2-52, University of Berkeley. , . , . , . , , . , . : .. , , .Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> , , , , Pentium 4</p> <p>Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> ;</p> <p> . , .19/10/08CS252-s06, Lec 01-intro</p> <p>3</p> <p>, , </p> <p> Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> (1) assembly</p> <p> ( ) </p> <p> . () .Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> (2) </p> <p> Assembler, Linker Firmware . . . I/O </p> <p> Assembly</p> <p> / </p> <p> 6</p> <p>cslab@ntua 2007-2008</p> <p> Assembly Assembly, 0000 1010 1100 0101</p> <p>temp=v[k]; v[k]=v[k+1]; v[k+1]=temp;</p> <p>load$15,0($2) load$16,4($2) store$16,0($2) store$15,4($2)1001 1111 0110 1000 1100 0101 1010 0000 0110 1000 1111 1001 1010 0000 0101 1100 1111 1001 1000 0110 0101 1100 0000 1010 1000 0110 1001 1111</p> <p>ISA</p> <p>, Control Signal Specificationcslab@ntua 2007-2008</p> <p>ALUOP[0:3] &gt; &gt; 2. Bottom Up &gt; &gt; &gt; * (Hardware/Software Co-design) * (Backward Compatibility)</p> <p>14cslab@ntua 2007-2008</p> <p>, (). = , , , , , = , , = , () , ..15cslab@ntua 2007-2008</p> <p> (1)Time = I x CPI x Clock Cycle Time- I: Instrumentation ( , ) - CPI: Cycles Per Instruction (, o) - Clock Cycle Time: ( ) , CPI Clock Cycle Time ( ) Clock Cycles = CPIi x i i: (CPIi) (i) .cslab@ntua 2007-2008</p> <p>16</p> <p> (2)FLOPs: Floating Point Operations per Second MIPs: Million Instructions per Second MIPs = / 106 /CPI X 106 1 ( ) : 1GHz, 1 GFLOP 1 , 1000MIPs</p> <p>4 x freq FLOPS &lt; {single Core 2 @ 2.93GHz} &lt; 8 x freq FLOPs , FPADD, FPMUL, FPDIV ( ). 12 GFLOPs/cpu17cslab@ntua 2007-2008</p> <p> (3)SPEC Benchmark () www.spec.org i execution ratio (ER) ERi=( 300 MHz UltraSun 5_10 / )* 100 Execution Ratios n ______ SpecRatio = (ERi) i=1,2,..,n - SPEC CPU2006: 12 integer 17 floating point - SPECThroughput, SPECJava... 18cslab@ntua 2007-2008</p> <p>TOP 500, 13/06/08</p> <p>19cslab@ntua 2007-2008</p> <p> ()* Patterson &amp; Hennessy, Computer Organization and Design , . '' .. MIPS. .</p> <p>* Bryant, O'Hallaron, Computer Systems: A Programmer's Perspective . '' .. 32. . .</p> <p>* Tanenbaum, Structured Computer Organization , , . . .. . .</p> <p>*Hamacher et.al., Computer Organization *Stallings, Computer Organization and Architecture. . .20cslab@ntua 2007-2008</p> <p> ()* Compus, httlp://compus.uom.gr , , , .</p> <p>* PdP Lab, http://www.it.uom.gr/teaching , , . Compus.</p> <p>* Wikipedia computer architecture . * Google..</p> <p>21cslab@ntua 2007-2008</p> <p> 1-2 3-5 6-8 9 10 11-12 13 , , .., (ssembly) 1,2,3 4 5 6 7 8 -</p> <p>22cslab@ntua 2007-2008</p> <p> . (. , ). ' : ', 4 5 - 6,7 8. 1,2 3, . , . MIC-1. Intel gcc, gdb / ddd (Linux). / (+20%).23cslab@ntua 2007-2008</p> <p> , , , , Pentium 4</p> <p>Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> : , , (1945) (1950) (1960) (1970) (1985) : , , (2000) (VLSI) </p> <p>Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> (1)</p> <p> .Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> (2)</p> <p> .Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> (1642 1945) (1945 1955) -Transistors (1955 1965) (1965 1980) -VLSI (1980 ?)</p> <p>Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p>19/10/08</p> <p>EDSAC, University of Cambridge, UK, 1949CS252-s06, Lec 01-intro</p> <p>29</p> <p> Von Neumann. bit-level . .Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> PDP-8. (). -.Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> IBM 360: . . .Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> - ( Intel). ( PC) (). (Miscrosoft MSDOS) (3rd parties). VLSI: , . - . : - .Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0 Tanenbaum, Structured</p> <p> Moore (1)</p> <p>(K) (LSI, VLSI). Moore 60% transistors chip. bits.Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> Moore (2): 2X 1.5 . ~1000X 10. : DRAM : &gt; 2x 1.5 . ~1000X 10. bit: 25% . : : &gt; 2X 1.5 . bit: 60% . 200X 10.35cslab@ntua 2007-2008</p> <p>.. Sensor Nets TIFF (Uncompressed) decompressor QuickTime see this picture. are needed toand a Cameras Games QuickTime Set-top and a TIFF (Uncompressed) decompressor are needed to see this picture. boxes Media Players Laptops ServersQuickTime and a TIFF (Uncompressed) decompressor are needed to see this picture.QuickTime_ and a TIFF (Uncompressed) decompressor are needed to see this picture.</p> <p>Smart phones Automobiles19/10/08</p> <p>Routers</p> <p>Robots</p> <p>Supercomputers 36</p> <p>CS252-s06, Lec 01-intro</p> <p> , .Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> - Pentium 4 Intel (-32) - UltraSPARC III Sun Microsystems - 8051 chip Intel, - PS, - ARM, - PIC, ? : .Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p>Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> , , , , Pentium 4</p> <p>Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> (PC)</p> <p> .Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p>'' </p> <p> (, ) CPU I/OTanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> CPUAddress Content00..0 01100..0</p> <p>MAR, MDR PC, IR</p> <p>FF..F</p> <p>0100..0</p> <p>Memory</p> <p>CPU</p> <p> ( ) CPU = , ALU, .Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> (Program Counter, PC) (Instruction Register, IR) (Memory Address Register, MAR) (Memory Data Register, MDR) (Accumulator, AC) , , C... (Stack Pointer, SP) Index, Base, Offset Registers (Status Register, SR)Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> - A. B. C. D. , () CPU E. () CPU F. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> (1)</p> <p>...</p> <p> ( Java).Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> (2)</p> <p> ( Java).Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> : . . -ROM.</p> <p> . ( ). . / ( ).</p> <p> ( -ROM )</p> <p>Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> T CPU </p> <p> (1-address)</p> <p> . - . ( ).</p> <p> (0-address)</p> <p> ( ) (Push, Pop). , . JVM.</p> <p> (0,1,2-address)</p> <p> . ( ) . ( RISC, CISC)Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> AC</p> <p>Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> ACint x, y, z; x = y + z; load 0xA2 add 0xA4 store 0xA0 0100 1010 0010 0110 1010 0100 0101 1010 0000 Assembly // AC := AC + mem(0xA4) </p> <p>IR := MDR(PC); PC := PC + len(instr); Decode (Opcode(IR); MAR := Operand(IR);AC := MDR(MAR);</p> <p> = </p> <p>Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> Stack</p> <p>Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> Stackint x, y, z; x = y + z; load 0xA2 load 0xA4 add store 0xA0 push 0xA2 push 0xA4 pop 0xA0 Assembly // pop, pop, add, push</p> <p>0100 1010 0010 0100 1010 0100 0110 0101 1010 000</p> <p>Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> Regs</p> <p>Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> Regsint x, y, z; x = y + z; `` load A, 0xA2 load B, 0xA4 add C, A, B store C, 0xA0 Assembly load A, 0xA2 add C, A, OxA4 store C, 0xA0 add C, 0xA2, 0xA4 store C, 0xA0 add 0xA0, 0xA2,0xA4</p> <p>0100 0000 1010 0010 0100 0001 1010 0100 0110 0010 0000 0001 0101 0000 1010 0000</p> <p> ; , ;</p> <p>Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> T </p> <p> (/ /) , , ( PC) ( ) /'o /</p> <p>Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> : Top 10 Intel X86 Instructions 1 2 3 4 5 6 7 8 9 10 load conditional branch compare store add and sub move register-register call return Total 22% 20% 16% 12% 8% 6% 5% 4% 1% 1% 96%57</p> <p>: .cslab@ntua 2007-2008</p> <p>RISC CISC (VAX). (200-300 ). - . Complex Instruction Set Computer (CISC) . . , ' . .. . - '' . Reduced Instruction Set Computer (RISC) .. . (MIPS, SPARC, PowerPC, ..) ? RISC (Pentium, ..) ? CISC RISC ( ..).Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> ' ( ). CPU ( , ILP). ( ). , Load, Store . ( register file).</p> <p>Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> (Data Level Parallelism, DLP): , ALU, , (32/64 bits, GPU). (Instruction Level Parallelism, ILP): ( , ). (Task/Thread Level Parallelism, Multithreading): (). (Functional Parallelism): ( GPU, DMA, I/O ..) / (Multiprocessors, Multicomputers): .Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> (ILP) CPU, - . , PC A 1 C D E Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p>2</p> <p>3</p> <p>4</p> <p>5</p> <p>6</p> <p>7</p> <p>8</p> <p>9</p> <p>10</p> <p> (ILP) Pipelining (, )</p> <p>() () .</p> <p>Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> (ILP) (Superscalar) (1)</p> <p> ( Pentium, ).</p> <p>Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> (ILP) (Superscalar) (2)</p> <p> , (Pentim II).Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> (ILP) (Superscalar) (3)</p> <p>1 C D1 D2 D3 D4 D5 E </p> <p>2</p> <p>3</p> <p>4</p> <p>5</p> <p>6</p> <p>7</p> <p>8</p> <p>9</p> <p>10</p> <p>Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> 96 bit.Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> Bytes (1)</p> <p>(a) Big endian (b) Little endian</p> <p>Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> Bytes (2)</p> <p>(a) big endian. (b) little endian. (c) big endian little endian. (d) bytes (c).Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> (Cache) (1)</p> <p> () cache CPU .</p> <p>Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> (Cache) (2)</p> <p> () , cache (L1/2/3) , (, ).</p> <p> . : : , . : </p> <p> : , : .</p> <p> Cache L1 &gt; K L2 &gt; L3 &gt; . L1 &lt; L2 &lt; L3 &lt; . L1 &lt; L2 &lt; L3 &lt; . Cache &lt; 1% : * Cache ( ). * Cache , . * Cache .</p> <p>L1 Instruction/Data on chip L2 on chip package L3 on board</p> <p>*</p> <p>*Virtual memory</p> <p>* /</p> <p> ( ) . ( *).Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> (1)</p> <p> .Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> (2) (Data Bus): MDR,IR, AC (A, B, C, ...) (Address Bus): MAR, PC, SP, Index,, Base (Control Bus): ..</p> <p> masters slaves .</p> <p>Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> (1)</p> <p> .Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> (2)</p> <p> .</p> <p>Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> (1)</p> <p>(a) . (b) .Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0</p> <p> (2)</p> <p> .</p> <p>Tanenbau...</p>