etri-asic design intro - Here is 2 ASIC 회로설계입문 r차 례r ASIC 개요 IC 분류, What is ASIC?, Why ASIC? What is Semiconductor?, 집적기술의발전 설계표현 ASIC화를위한검토사항 설계사양은확정되었는가? 설계환경은갖추었는가? ASIC을제작

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  • ETRI ASIC

    ASIC

  • 2ETRI ASIC

    r r

    ASIC IC , What is ASIC?, Why ASIC? What is Semiconductor?,

    ASIC ? ? ASIC?

    ASIC

  • 3ETRI ASIC

    r r

    , ASIC , , 1996

    , VLSI , , 1997 7

    J.Schroeter, Surviving the ASIC Experience, Prentice Hall, 1992

    Douglas J Smith, HDL Chip Design, Doone Publications, 1996

    D. A. Pucknell et al, Basic VLSI Design, Prentice Hall, 1994

    T. Williams., VLSI Testing, North-Holland Publishers, 1986

    Watts, R.K., Submicron Integrated Circuits, John Wiley and Sons Inc., New York, 1989

    Sze, S. M., Semiconductor Devices: Physics And Technology, Bell Telephone Laboratories, USA., 1985

    Douglas J Smith, HDL Chip Design, Doone Publications, USA., 1996

  • 4ETRI ASIC

    ASIC

    r IC

    Standard IC

    Memory Microprocessor DSP TTL

    ASIC( Custom IC)

    Full Custom Semi-Custom

    - SOG(Sea Of Gate)- CBIC(Cell Base IC i.e. Standard Cell)

    PLD- SPLD: PAL(Programmable Array of Logics)- CPLD: PAL- FPGA(Field Programmable Gate Array)

    ASSP

    SOC(System On a Chip) : IP(Intellectual Property)

  • 5ETRI ASIC

    ASIC

    rWhat is ASIC?

    Application Specific Integrated Circuit

    System IC

    Non-Memeory IC

    Implementation of an Application Specific Algorithm on a Silicon

    Many Definitions Possible(Software)

    SoC(System on a Chip)

    - Level0- Level1- Level2- Level3

  • 6ETRI ASIC

    ASIC

    rWhy ASIC?

    Cost Reduction

    Area Reduction

    Protecting IP

    High Performance

    High Reliability

    Low Power Consumption

  • 7ETRI ASIC

    ASIC

    rWhat is Semiconductor?

    Conductor

    Insulator

    Semiconductor

    Energy Gap- Si: 1.1eV, Ge: 0.67eV

    Electron-Hole Pair

    PN Junction(Diode)

    PNP(or NPN) Transistor- Bipolar Transistor- CMOS Transistor- BiCMOS Transistor- Compound Material Transistor

    . MESFET

  • 8ETRI ASIC

    ASIC

    r

    P6P5

    i860

    i486

    i80286

    HP32

    i43201

    i8087

    i8086

    i8080

    i4004

    104

    105

    106

    107

    7570 80 85 90 95 2000

    105

    106

    107

    108

    109

    64K

    256K

    1M

    4M

    16M

    64M

    256M

    DR

    AM

    /

  • 9ETRI ASIC

    ASIC

    r Hierachical Representation

    Top-down Bottom-up(library-base)

    B

    A

    C

    D E F G H

    H J I J

  • 10ETRI ASIC

    ASIC

    r

    (a) C

    #include main( ){ int input,ouput; ... output=!input; ...}

    0 11 0

    (b)

    Vinv

    Vin

    (c)

    Vout

    (e) (f)

    (d)

  • 11ETRI ASIC

    ASIC

    r??

    ASIC? Digital ASIC? Analog ASIC? IP?

    Application System?

    I/O Pin ?

    r ASIC? ASIC Foundry?

    ASIC Test?

    ASIC ?

    ASIC Tool?

    ASIC Foundry Design Kit?

    Performance Technology?

  • 12ETRI ASIC

    ASIC

    rASIC

    Chip

    Chip

    Chip

    Proto-Type

    Chip

  • 13ETRI ASIC

    ASIC

    rASIC Design Flow(Front-End)

    ASIC

    VHDL Coding

    VHDL Simulation

    Synthesis

    Test Vector Gen.

    Pre-Simulation

    Fault Simulation

    Schematic Entry

    Test Vector Gen.

    Pre-Simulation

    Fault Simulation

    Verified Netlist

  • 14ETRI ASIC

    ASIC

    rASIC Design Flow(Back-End)

    Verified Verified NetlistNetlist

    P&R Seed FileP&R Seed File

    P&RP&R

    Cap. Net. ExtractCap. Net. Extract

    PostPost--SimulationSimulation

    Merge PhantomMerge Phantom

    DRC, LVSDRC, LVS

    GDS FileGDS File

  • 15ETRI ASIC

    ASIC

    r ASIC Chip Mask

    MASK

    : : :

    ASIC

    CIFGDS

    MEBES

    MASK

    Tool CATSDRACULAMASK

  • 16ETRI ASIC

    ASIC

    r 3

    1. . . CVD(Chemical Vapor Deposition) : Poly-Silicon, , , (), PSG(Phosphorus Silica Glass). PVD(Physical Vapor Deposition) : Al, Silicide

    2. Photo Etch . Lithography

    - Photo Resist -(Expose) : UV -(Develop)- Photo Resist : (Negative Resist)

    . Etch -- Photo Resist

    3. . : (900-1000C)(Furnace)

    .

  • 17ETRI ASIC

    ASIC

    MOSFET 1. Wafer 2. : 3. Channel Stop (NMOSFET B )4. LOCOS ()5. 6. (SiO2) 7. Threshold Voltage Control8. ( Poly-Silicon)9. 10. Source, Drain 11. Metal12. Contact 13. 1st Metal 14. 1st Metal to 2nd Metal 15. 2nd Metal Via 16. 2nd Metal 17. (Passivation) 18. Pad 19. Wafer Test Line20. Inking Sawing21. Package Line22. Package Test

    Metal 1, 2 Al 3, 4

  • 18ETRI ASIC

    ASIC

    r ASIC ASIC Military Industrial Commercial

    ASIC

    ASIC Tool

    ASIC Chip (Full Custom, CBIC, SOG) (Macro Cell, Mega-Cell) (Design Rule)

    Package

    System System Block Diagram System Description

    ASIC Block ASIC Block Diagram ASIC Description Timing(Truth Table)

  • 19ETRI ASIC

    ASIC

    -- Voltage Level- Pull Up/Pull Down -

    - Input Level- Reference Signal (Reference Signal )- Setup Time Margin- Hold Time Margin- Package Pin Number- Die Pad Number- Active (Active Low?, Active High?)- Pad Cell Name

    - Output Level- Propagation Delay- Sink Current- Source Current- Open Drain/Collector - Tristate - Package Pin Number- Die Pad Number- Pad Cell Name

  • 20ETRI ASIC

    ASIC

    (BiDirectional) - Control (Control Mode(I/O)?)- Input, Output Level- Sink Current- Source Current- Propagation Delay- Package Pin Number- Die Pad Number- Tristate?- Open Drain/Collector?- Pad Cell Name

    Clock - Asynchronous Clock- Clock- Clock Duty Cycle- Crystal Type Oscillator Type- Package Pin Number- Die Pad Number

  • 21ETRI ASIC

    ASIC

    r Testable Design Testability : Test Vector Fault Cover Controllability

    - Clock Signals- Control Signals(Preset, Clear, Enable, Hold)- Select Signals(Data Select, Data Bus, Address Bus)

    Observability- Control Signals- Data Lines of Storage Devices(Flip Flops, Counters, Shift Register, RAM, ROM)- Global Feedback Path- Data Output of Combinational Logic Devices(Encoders, Multiplexers, Parity Generators)

    DFT(Design For Testability) Ad-Hoc DFT Techniques : Testability Test Circuit

    1) Test Points : Decoder, Multiplexer, Shift Register Design Testable Design.

    - Logic Critical Path Test Point.- Test Point- Controllability Test Point- Observability Test Point- Fan-Out Test Point.- Logic Test Point.

    2)Initialization : Master Reset- Flip Flop Clear

    Initialization

  • 22ETRI ASIC

    ASIC

    3) Oscillators and Clocks: Tester Clock Circuit.

    Free Running Internal Clock,

    4) Partition: 24 Bit Counter, 10 Bit Divider.

    5) Logical Redundancy- Logical Redundancy : Output Value Input Fault Cover

    6) Global Feedback Path- Local Feedback Loop : Gate Output Gate Input

    - Global Feedback Loop: Gate Output Loop Gate Input Feedback

    7) Scan Design: Shift Register Test Data Test Sequential Logic Combinational Logic.- Level Sensitive Scan Design(LSSD)- Edge Sensitive Scan Design- Random Access Scan

  • 23ETRI ASIC

    ASIC

    r Core Library Foundry Library

    ) 1. Combinational Logic(AND, OR, NAND, NOR, )2. Sequential Logic(Latch, Flip Flop)3. Foundry Dependent Cells(Repeater, Level Shifter, )

    Library- Mega-Cell- Foundry - Memory(RAM, ROM)- CPU Library- Analog Library(Standard Cell)- IP(Intellectual Property)

    Design Core Library

    Library, .

    Technology Independent ,

    HDL(Synthesis)

    Test

  • 24ETRI ASIC

    ASIC

    r I/O Library Foundry I/O Library(Pad Library)

    1) Input Pad Library2) Output Pad Library3) Bidirectional Pad Library4) Tri-State Pad Library5) Clock Library : Oscillator, Crystal Pad Library

    Level Sensing Library1) TTL Level Shifter2) CMOS Level Shifter

    Slew Rate Pad Library

    Pull Up, Pull Down Pad Library

    Open Drain Pad Library

    Schmitt Trigger Library

    Output Current Library

    Power Pad Library

    Ground Pad Library

  • 25ETRI ASIC

    ASIC

    r ASIC Tool(Work Station Version) : Digital Schematic Entry Tool Foundry Library Transistor Best Case, Typical Case, Worst Case

    Entry Schematic Check

    Simulator Modeling Logic Simulation User Interface User Friendly Tool() Interface(Post P&R )

    Back End Design Tool Floor Planning Placement & Routing(Automatic) RC Extraction Design Rule Check Layout Verification(LVS) CIF and GDS Generation Tool

    HDL Tool HDL Simulator(Behavioral Simulator) HDL Analysis Synthesis

  • 26ETRI ASIC

    ASIC

    Tool Gate Count Critical Path Buffering Delay Calculation Test Support : Test Vector Generation & Confirmation Toggle Check Fault Simulator(ZYCAD) Power Calculation Bonding Tool Hardware Accelerator Mega-Cell Compiler Hardware Emulator(QUICKTURN, IKOS) Algorithm Design

    FPGA Design Tool ALTERA XILINX ACTEL QUICKLOGIC LATTICE AT&T

  • 27ETRI ASIC

    ASIC

    r CMOS TTL I/O

    CMOS TTL Interface

    Sink Current = IIL(0.4mA) X Fanout

    Sink Current Source Current Speed (Delay )

    Digital ASIC Sink Current Source Current(, 2mA Output Pad Sink Current Source Current 2mA)

    Source

    Sink

    IIL

    IIH

  • 28ETRI ASIC

    ASIC

    CMOS TTL I/O

    Slew Rate Schmitt Trigger

  • 29ETRI ASIC

    ASIC

    r Noise Margin

    CMOS VOHmin = 4.5V VIHmin = 3.5VVOLmax = 0.4V VILmax =