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<ul><li><p>Field Effect TransistorsField Effect TransistorsCHAPTER 6</p></li><li><p>IntroductionIntroduction Two main types of FET:</p><p>- JFET Junction field effects transistor- MOSFET Metal oxide semiconductor field effect transistor</p><p>- D-MOSFET ~ Depletion MOSFET- E-MOSFET ~ Enhancement MOSFET</p><p> Similarities:-Amplifiers-Switching devices-Impedance matching circuits</p><p> Differences:-FETs are voltage controlled devices whereas BJTs are currentcontrolled devices.-FETs also have a higher input impedance, but BJTs have highergains.-FETs are less sensitive to temperature variations and more easilyintegrated on ICs.- FETs are also generally more static sensitive than BJTs.</p></li><li><p>Construction and characteristics of JFETConstruction and characteristics of JFET</p><p> N-channel device will appear as theprominent device with paragraph andsection devoted to the impact of using ap-channel.</p><p> Major part of structure is n-type material. Top of the n-type channel is connected</p><p>through an ohmic contact to a terminalreferred to as the drain (D)</p><p> The lower end-connected through anohmic contact to a terminal referred assource (S)</p><p> P-type materials are connected togetherand to the gate (G) terminal.</p><p> JFET has two p-n junctions under no-biasconditions.</p></li><li><p>Construction and characteristics of JFETConstruction and characteristics of JFET</p><p> JFET operation can be compared to a water spigot:</p><p> The source of water pressure accumulated electrons at the negative pole ofthe applied voltage from Drain to Source</p><p> The drain of water electron deficiency (or holes) at the positive pole of theapplied voltage from Drain to Source.</p><p> The control of flow of water Gate voltage that controls the width of the n-channel, which in turn controls the flow of electrons in the n-channel fromsource to drain.</p></li><li><p>N-Channel JFET Circuit Layout</p><p>Construction and characteristics of JFETConstruction and characteristics of JFET</p></li><li><p>JFET Operating CharacteristicsJFET Operating Characteristics</p><p>There are three basic operating conditions for a JFET:</p><p>A. VGS = 0, VDS increasing to some positive</p><p>value</p><p>B. VGS &lt; 0, VDS at some positive value</p><p>C. Voltage-Controlled Resistor</p></li><li><p>VVGSGS == 00, V, VDSDS increasing to some positiveincreasing to some positivevaluevalue</p><p>Three things happen when VGS = 0</p><p>and VDS is increased from 0 to a</p><p>more positive voltage:</p><p> the depletion region between p-gate and n-channel increases as electrons from n-channelcombine with holes from p-gate.</p><p> increasing the depletion region, decreasesthe size of the n-channel which increases theresistance of the n-channel.</p><p> But even though the n-channel resistance is</p><p>increasing, the current (ID) from Source to</p><p>Drain through the n-channel is increasing. This</p><p>is because VDS is increasing.</p></li><li><p>VVGSGS == 00, V, VDSDS increasing to some positiveincreasing to some positivevaluevalue The flow of charge is relatively uninhibited and limited solely by</p><p>the resistance of the n-channel between drain and source.</p><p> The depletion region is wider near the top of both p-typematerials.</p><p> ID will establish the voltage level through the channel.</p><p> The result: upper region of the</p><p>p-type material will be reversed biased by</p><p>about 1.5V with the lower region only</p><p>reversed biased by 0.5V (greater</p><p>applied reverse bias, the wider</p><p>depletion region).</p></li><li><p>VVGSGS == 00, V, VDSDS increasing to some positiveincreasing to some positivevaluevalue IG=0A p-n junction is reverse-biased for the length of the</p><p>channel results in a gate current of zero amperes.</p><p> As the VDS is increased from 0 to a few volts, the current will</p><p>increase as determined by Ohms Law.</p><p> VDS increase and approaches a level referred to as Vp, the</p><p>depletion region will widen, causing reduction in the channel</p><p>width. (p large, n small).</p><p> Reduced part of conduction causes the resistance to increase.</p><p> If VDS is increased to a level where it appears that the 2 depletion</p><p>regions would touch (pinch-off)</p></li><li><p>VVGSGS == 00, V, VDSDS increasing to some positiveincreasing to some positivevaluevalue</p><p> Vp = pinch off voltage.</p><p> ID maintain the saturation level defined as IDSS Once the VDS &gt; VP, the JFET has the</p><p>characteristics of a current source.</p><p> As shown in figure, the current is fixed at ID =</p><p>IDSS, the voltage VDS (for level &gt;Vp) is determined</p><p>by the applied load.</p><p> IDSS is derived from the fact that it is the drain-</p><p>to-source current with short circuit connection</p><p>from gate to source.</p><p> IDSS is the max drain current for a JFET and is</p><p>defined by the conditions VGS=0V and VDS &gt; |</p><p>Vp|.</p></li><li><p>VVGSGS == 00, V, VDSDS increasing to some positiveincreasing to some positivevaluevalue</p><p>At the pinch-off point:</p><p>any further increase in VGS does</p><p>not produce any increase in ID.</p><p>VGS at pinch-off is denoted as Vp.</p><p> ID is at saturation or</p><p>maximum. It is referred to as IDSS.</p><p> The ohmic value of the channelis at maximum.</p></li><li><p>Typical JFET operationTypical JFET operation</p></li><li><p>JFET modeling when ID=IDSS, VGS=0, VDS&gt;VP</p></li><li><p>VVGSGS </p></li><li><p>VGS </p></li><li><p>VGS </p></li><li><p>Characteristic curves for NCharacteristic curves for N--channel JFETchannel JFET</p></li><li><p>VoltageVoltage--Controlled ResistorControlled Resistor</p><p> The region to the left of the pinch-off point is called the ohmic region.</p><p> The JFET can be used as a variable</p><p>resistor, where VGS controls the</p><p>drain-source resistance (rd). As VGSbecomes more negative, the</p><p>resistance (rd) increases.</p><p>2</p><p>P</p><p>GS</p><p>od</p><p>)V</p><p>V(1</p><p>rr</p></li><li><p>And as summary in practicalAnd as summary in practical</p></li><li><p>pp--Channel JFETSChannel JFETS</p><p>p-Channel JFET acts the same as the n-channel JFET,except the polarities and currents are reversed.</p></li><li><p>PP--Channel JFET CharacteristicsChannel JFET Characteristics</p><p>As VGS increases more positively:</p><p> the depletion zone increases</p><p> ID decreases (ID &lt; IDSS)</p><p> eventually ID = 0A</p><p>Also note that at high levels of</p><p>VDS the JFET reaches a</p><p>breakdown situation. ID</p><p>increases uncontrollably if</p><p>VDS&gt; VDSmax.</p></li><li><p>JFET SymbolsJFET Symbols</p></li><li><p> There is a convenient relationship between IDS and VGS. Beyond pinch-off</p><p> Where IDSS is drain current when VGS= 0 and VGS(off) isdefined as VP, that is gate-source voltage that justpinches off the channel.</p><p> The pinch off voltage VP here is a +ve quantity because itwas introduced through VDS(sat).</p><p> VGS(off) however is negative, -VP.</p><p>2</p><p>)(</p><p>1</p><p>offGS</p><p>GSDSSDS</p><p>V</p><p>VII</p></li><li><p>II--V characteristicsV characteristics</p></li><li><p>II--V characteristicsV characteristics</p></li><li><p>The transconductance curveThe transconductance curve</p><p> The process for plotting trans-conductancecurve for a given JFET:</p><p> Plot a point that corresponds to value ofVGS(off).</p><p> Plot a point that corresponds to value ofIDSS.</p><p> Select 3 or more values of VGS between 0 Vand VGS(off). For value of VGS, determine thecorresponding value of ID from</p><p> Plot the point from (3) and connect all theplotted point with a smooth curve.</p></li><li><p>Transfer CharacteristicsTransfer Characteristics</p><p> The transfer characteristic of input-to-output is not asstraight forward in a JFET as it was in a BJT.</p><p> In a BJT, indicated the relationship between IB (input)and IC (output).</p><p> In a JFET, the relationship of VGS (input) and ID (output) isa little more complicated:</p><p>2</p><p>P</p><p>GSDSSD )</p><p>V</p><p>V(1II </p></li><li><p>Transfer CharacteristicsTransfer Characteristics</p><p>Transfer Curve</p><p>From this graph it is easy to determine the value of ID for a given value of VGS.</p></li><li><p>Plotting the Transfer CurvePlotting the Transfer CurveShockleys Equation Methods. Using IDSS and Vp (VGS(off)) values found in a specification sheet, the</p><p>Transfer Curve can be plotted using these 3 steps:</p><p> Step 1:</p><p> Solving for VGS = 0V:</p><p> Step 2:</p><p> Solving for VGS = Vp (VGS(off)):</p><p> Step 3:</p><p> Solving for VGS = 0V to Vp:</p><p>2</p><p>P</p><p>GSDSSD )</p><p>V</p><p>V(1II </p><p>0VVII</p><p>GSDSSD</p><p>2</p><p>P</p><p>GSDSSD )</p><p>V</p><p>V(1II </p><p>PGSD</p><p>VV0I</p><p> A</p><p>2</p><p>P</p><p>GSDSSD )</p><p>V</p><p>V(1II </p></li><li><p>Plotting the Transfer CurvePlotting the Transfer Curve</p><p>Shorthand method</p><p>VGS ID</p><p>0 IDSS</p><p>0.3VP IDSS/2</p><p>0.5 IDSS/4</p><p>VP 0mA</p></li><li><p>Specification Sheet (JFETs)</p></li><li><p>This information is also available on the specification sheet.</p><p>Case Construction and Terminal Identification</p></li><li><p>MOSFETsMOSFETs</p><p>MOSFETs have characteristics</p><p>similar to JFETs and additional</p><p>characteristics that make them</p><p>very useful.</p><p>There are 2 types:</p><p>1. Depletion-Type MOSFET</p><p>2. Enhancement-Type MOSFET</p></li><li><p>DepletionDepletion--Type MOSFET ConstructionType MOSFET Construction</p><p>The Drain (D) and Source (S) connect to the to n-doped regions. These N-</p><p>doped regions are connected via an n-channel. This n-channel is connected</p><p>to the Gate (G) via a thin insulating layer of SiO2. The n-doped material lies</p><p>on a p-doped substrate that may have an additional terminal connection</p><p>called SS.</p></li><li><p>DepletionDepletion--Type MOSFETType MOSFETConstructionConstruction</p><p> VGS is set to 0V by the direct</p><p>connection from one terminal to</p><p>the other.</p><p> VDS is applied across the drain-to-</p><p>source terminals.</p><p> The result is an attraction for the</p><p>positive potential at the drain by the</p><p>free electron of the n-channel and a</p><p>current similar to that established</p><p>through the channel of the JFET.</p><p> In the figure, VGS has been set at a</p><p>negative voltage (-1V)</p></li><li><p>DepletionDepletion--Type MOSFETType MOSFETConstructionConstruction</p><p> Negative potential at gate will tend to pressureelectron towards the p-type substrate andattract holes from the p-type substrate.</p><p> Depending on negative bias established byVGS, a level recombination betweenelectron and hoes will occur.--- it willreduce the number of free electron in then-channel available for conduction.</p><p> The more negative bias, the higher therate of recombination</p><p> ID decrease, negative bias for VGS increase</p></li><li><p>Basic OperationBasic Operation</p><p>A Depletion MOSFET can operate in two modes: Depletion or Enhancement mode.</p></li><li><p>DepletionDepletion--type MOSFET in Depletiontype MOSFET in DepletionModeMode</p><p>Depletion modeThe characteristics are similar to theJFET.When VGS = 0V, ID = IDSSWhen VGS &lt; 0V, ID &lt; IDSSThe formula used to plot the TransferCurve still applies:</p><p>2</p><p>P</p><p>GSDSSD )</p><p>V</p><p>V(1II </p></li><li><p>DepletionDepletion--type MOSFET in Enhancementtype MOSFET in EnhancementModeMode</p><p>Enhancement modeVGS &gt; 0V, ID increases above IDSSThe formula used to plot theTransfer Curve still applies:</p><p>(note that VGS is now a positivepolarity)</p><p>2</p><p>P</p><p>GSDSSD )</p><p>V</p><p>V(1II </p></li><li><p>pp--Channel DepletionChannel Depletion--Type MOSFETType MOSFET</p><p>The p-channel Depletion-type MOSFET is similar to the n-channel exceptthat the voltage polarities and current directions are reversed.</p></li><li><p>SymbolsSymbols</p></li><li><p>EnhancementEnhancement--Type MOSFET ConstructionType MOSFET Construction</p><p>The Drain (D) and Source (S) connect to the to n-doped regions.These n-doped regions are connected via an n-channel. TheGate (G) connects to the p-doped substrate via a thin insulatinglayer of SiO2. There is no channel. The n-doped material lies</p><p>on a p-doped substrate that may have an additional terminalconnection called SS.</p></li><li><p>EnhancementEnhancement--Type MOSFETType MOSFETConstructionConstruction</p><p> VGS=0, VDS some value, the absence of an n-channel will result in acurrent of effectively 0A</p><p> VDS some positive voltage, VGS=0V, and terminal SS is directlyconnected to the source, there are in fact 2 reversed-biased p-njunction between the n-doped regions and p substrate to opposeany significant flow between drain and source.</p><p> VDS and VGS have been set at some positive voltage greater than 0V,establishing the D and G at a positive potential with respect to thesource</p><p> The positive potential at the gate will pressure the holes in the psubstrate along the edge of the SiO2 layer to leave the area andenter deeper regions of the p-substrate</p><p> The result is a depletion region near the SiO2 insulating layer voidof holes</p></li><li><p>EnhancementEnhancement--Type MOSFETType MOSFETConstructionConstruction</p><p> The electrons will in the p substrate will be attracted to</p><p>the +G and accumulate in the region near the surface</p><p>of the SiO2 layer</p><p> The SiO2 layer and its insulating qualities will prevent</p><p>the negative carriers from being absorbed at the gate</p><p>terminal</p><p> VGS increase, the concentration of electrons near theSiO2 surface increase until eventually the induced n-type region can support a measurable flow between Dand S</p><p> The level of VGS that results in the significant increasein drain current is called the threshold voltage, VT.</p><p> VGS increase beyond the VT level the density of thecarriers in the induced channel will increase and ID alsoincrease</p></li><li><p>EnhancementEnhancement--Type MOSFETType MOSFETConstructionConstruction</p><p> If VGS constant and increase the</p><p>level of VDS, ID will eventually reach</p><p>a saturation level as occurred for</p><p>the JFET</p><p> Applying Kirchoffs voltage law tothe terminal voltage of the MOSFET</p><p>VDG = VDS- VGS</p><p> If VGS fixed at some value, 8V, VDSincreased from 2 5V, the VDG willdrop from -6V to -3V and the gatewill become less and less positivewith respect to the drain</p></li><li><p>EnhancementEnhancement--Type MOSFETType MOSFETConstructionConstruction</p><p>VGS is always positiveAs VGS increases, ID increasesBut if VGS is kept constant and VDS is</p><p>increased, then ID saturates (IDSS)</p><p>The saturation level, VDSsat isreached.</p><p>TGSDsat VVV </p><p>The Enhancement-type MOSFET only operates in the enhancement mode.</p></li><li><p>EnhancementEnhancement--Type MOSFETType MOSFETConstructionConstruction</p><p>To determine ID given VGS:</p><p>where VT = threshold voltage or voltage at which the MOSFET turns on.k = constant found in the specification sheet. k can also be determined byusing values at a specific point and the formula:</p><p>VDSsat can also be calculated:</p><p>2)( TGSD VVkI </p><p>2TGS(ON)</p><p>D(on)</p><p>)V(V</p><p>Ik</p><p>TGSDsat VVV </p></li><li><p>pp--Channel EnhancementChannel Enhancement--Type MOSFETsType MOSFETs</p><p>The p-channel Enhancement-type MOSFET is similar to the n-channel except that the voltage polarities and current directionsare reversed.</p></li><li><p>SymbolsSymbols</p></li><li><p>Specification SheetSpecification Sheet</p></li><li><p>MOSFET HandlingMOSFET Handling</p><p> MOSFETs are very static sensitive. Because of the verythin SiO2 layer between the external terminals and thelayers of the device, any small electrical discharge canstablish an unwanted conduction.</p><p>Protection: Always transport in a static sensitive bag</p><p> Always wear a static strap when handling MOSFETS</p><p> Apply voltage limiting devices between the Gate and Source,such as back-to-back Zeners to limit any transient voltage.</p></li><li><p>VMOSVMOS</p><p>VMOS Vertical MOSFET increases the surface area of thedevice.</p><p>Advantage:This allows the device to handle higher currents byproviding it more surface area to dissipate the heat.</p><p>VMOSs also have faster switching times.</p></li><li><p>CMOSCMOSCMOS Complementary MOSFET p-channel and n-channel MOSFET on the same</p><p>substrate.</p><p>Advantage:</p><p>Useful in logic circuit designs</p><p>Higher input impedance</p><p>Faster switching speeds</p><p>Lower operating power levels</p></li><li><p>Summary TableSummary Table</p></li></ul>