Gioi Thieu VHDL

  • Published on

  • View

  • Download

Embed Size (px)


tng quan v VHDL cho cc bn


<ul><li><p>Thit k mch s vi<br />VHDL</p></li><li><p>Kin thc trc y</p>H thng s:S v mMch t hpMch tun t (FF, mch m, my trng thi)CAD experience (Schematics?)Ngn ng lp trnhC ? Pascal ? BASIC ? Fortran ? Cobol ?HDL? </li><li><p>Mch S</p>Transistor CircuitsTR Circuit : Full-CustomGate/FlipFlop CellCell Library : Semi-Custom (SSI)Functional ModuleAdder, Multiplier, Register, Counter (LSI)Processor-MemoryProcessor, Memory (VLSI)SystemSOC (System-On-Chip)</li><li><p>Mch S</p></li><li><p>Cng c thit k mch s</p>Transistor CircuitLayout Editor &amp; Circuit/Switch SimulatorGate/FlipFlopSchematic Editor &amp; Logic SimulatorASICHardware Description Language (HDL)Verilog HDL/VHDLHDL &amp; Schematic Mixed</li><li><p>Ti sao s dng HDL?</p>Giam thi gian a san phm ra thi trngCho phep cac nha thit k phat trin nhng thit k ln oi hoi hang ngan cng logic.Cung cp mt h thng cp cao m ta cac mach logic phc tap.H tr phng phap thit k theo module va phng phap thit k a cp.Ngn ng dung thit k va m phongCho phep tao ra nhng thit k khng phu thuc vao linh kin cua mt hang nao. Rt tt cho vic thit k nhng IC chuyn dung (ASIC).Cho phep ngi s dung tuy chon cng cu, nha cung cp va linh kin.</li><li><p>HDL nh mt ngn ng lp trnh</p></li><li><p>HDL : l ngn ng?</p>Hardware Description LanguageStatementsSequentialConcurrentSyntaxKeywordsObjectsOperators</li><li><p>HDL : Hardware Description ?</p>Netlist/DataflowBehavior/Inference FF-- AND Gatea </li><li><p>So snh HDL V Ngn ng lp trnh</p>Ngn ng lp trnhHardware LanguagePurposeSoftware(Executable Binaries)Hardware(Hardwired Logics)EntryText &amp; Visual ToolsDevelopmentCompile &amp; LinkCompile for Simulation&amp; Synthesis for HardwireDebuggingExecutes &amp; View Result (Text or Graphics)Simulation &amp; ViewWaveformStatementSequential OnlyBasically ConcurrentSequential for BehaviorDescription</li><li><p>So snh HDL V Ngn ng lp trnh</p></li><li><p>HDL : Concurrent &amp; Sequential Statement</p>Th t statementObjects</li><li><p>S quy trong HDL</p>Pht biu quyLatch (cht)</li><li><p>Li li bi nhiu ng trong HDL</p></li><li><p>Quy tnh thit k vi HDL</p></li><li><p>Design Entry</p>Text EditorLanguage Sensitive Text EditorKeyword coloringStatement TemplateVisual Entry ToolsTemplate &amp; Translate (Structural)TestbenchConverter (Waveformer)</li><li><p>HDL Design Entry (Text Editor)</p></li><li><p>HDL &amp; Schematic Mixed</p></li><li><p>HDL Design Entry (Visual Tools)</p></li><li><p>HDL Simulation</p></li><li><p>HDL Synthesis</p>Ti u logicTng hp thnh netlist</li><li><p>VHDL l g?</p>VHSIC Hardware Description LanguageVHSIC : Very High Speed Integrated CircuitsBan u c xy dng cho vic lp ti liu cho cc thit k.Mt ngn ng m phng cho h thng s.Cu trc cp cao, v kiu d liu mnh.Mt ngn ng a dng.</li><li><p>VHDL : mt ngn ng a dng</p>M t tun t (Sequential Description)M t song song (ng thi) (Concurrent Description)Netlist LanguageTiming SpecificationSelf-Contained Test Language(TestBenches)</li><li><p>Lch s ca VHDL</p>First Generated in 1981 under VHSIC programDevelopment Started in 1983Maintained by IEEE since 1987(IEEE1076-87)MIL-STD-454 Requires VHDL for All ASICs Delivered to DoD (1988)IEEE1164: Multi Valued Logic System, 1992Revised Standard VHDL-93VITAL Initiative Defines Standard Format for Gate Libraries,1994</li></ul>