Multiple levels of metallization offer possibilities forcircuit designers to route signals over transistors, and thusto reduce the area needed for wiring. We will first discussmultilevel metallization for submicron technologies(0.8, 0.5, 0.35 and 0.25 m) based on aluminum wiringwith tungsten via plugs (Figure 28.1). The intermetal
Figure 28.1 Cross-sectional view of six-level metal struc-ture (M0 is metal zero). Reproduced from Koburger et al.(1995) by permission of IBM
dielectric is oxide, and it is planarized by CMP. We willthen delve into copper metallization which emerged inthe late 1990s. There CMP is used too, but this time topolish copper. While transistors get speedier the smallerthey are, metallization behaves differently: RC time de-lays increase with downscaling because thinner dielectricsincrease capacitance and narrower and thinner wires havehigher resistances.
28.1 Two-Level MetallizationTwo-level metallizations are extensions of one-level met-allizations, with additional dielectric and metal films andonly minor conceptual differences. The process continuesafter first metal as follows:
Process flow for two-level metallization
Intermetal dielectric deposition PECVD oxidePlanarization Spin-on-glass
with etchbackVia hole lithography and etching CHF3 plasma
oxide etchSecond metal deposition TiW/Al
sputteringSecond metal lithography and
etchingPassivation PECVD nitrideBonding pad patterning (litho
and etch)CF4 plasma etch
Introduction to Microfabrication, Second E dition Sami Franssila 2010 John Wiley & Sons, L td. ISBN: 978-0-470-74983-8
358 Introduction to Microfabrication
Contact hole etching of oxide against silicon demandsa highly selective etch process because both oxide andsilicon are etched by fluorine. Contacts between metallevels (known as via holes) are easier from an etchingpoint of view: fluorine-based oxide etching will stop auto-matically once aluminum is reached. Because there ismetal on the wafer, cleaning solutions after via etchingare limited. The second-metal step coverage in the viahole is often critical. Fortunately, via holes are largerthan contact holes, and aspect ratios are therefore smaller.
There are a number of practical aspects in two-levelmetal processes which demand attention. Each additional(PE)CVD step adds to thermal loads, film stresses andplasma damage. Aluminum lines experience thermalexpansion and are under compressive stresses. Thesestresses are relaxed by hillocks: protrusions of aluminumsticking out. Hillocks can sometimes be micrometers high.
Two-level metallization cannot be extended to threelevels because the topography of the wafer becomes morepronounced after each level, and the gap filling capabil-ity of (PE)CVD dielectric deposition as well as sputteringstep coverage in via holes will reach their limits. Pla-narization helps, but it is no panacea: the surface maybecome flat, which eliminates optical lithography depth-of-focus problems, but, as shown below in Figure 28.2,it creates problems in via hole etching and sputtering be-cause holes will be of different depth.
All devices need metallization, and logic circuits usu-ally require the most complex routing, while memoriessuffice with three levels of metal. Even superconductingdevices require multiple levels of metallization if they arecomplex logic circuits (Figure 28.3).
28.1.1 Spin-coated inorganic films
Spin-on-glasses (SOGs) are silicon-containing polymerswhich can be spun and then cured to produce a silicondioxide-like glassy material (they are sometimes knownas SODs, for spin-on dielectrics, which includes polymers,too). Numerous commercial formulations for SOGs exist,adjusted for molecular weight, viscosity and final filmproperties for specific applications. Two basic types ofSOGs are the organic and inorganic. The inorganic SOGsare silicate based and the organics are siloxane based.
Upon curing the reaction at about 400 C silicate SOGsturn into an oxide-like material which is thermally stableand does not absorb water accordingly. They are, how-ever, subject to volume shrinkage during curing, leadingto high stresses (400 MPa). This limits silicate SOGs tothin layers, about 100200 nm. Multiple coating/curingcycles can be used to build up thickness, at the cost ofquite an increase in the number of process steps. Addingphosphorus to SOG introduces changes similar to thephosphorus alloying of CVD oxide films. The resultingfilms are softer and exhibit less shrinkage, and are bet-ter in filling gaps. However, water absorption increases,which results in less stable films. The gap-filling capabil-ity of SOGs is related to viscosity: low viscosity equalsgood gap fill, but, unfortunately, it is correlated with highshrinkage, too.
Organic SOGs based on siloxane (Figure 28.4) do notresult in pure SiO2-like material, but contain carbon evenafter curing. By tailoring the carbon content, the materialproperties can be modified for lower stress (150 MPa)and consequently thicker films. Siloxane films are, how-ever, polymer-like in their thermal stability, and 400 Cis a practical upper limit.
7000 3000 8000 4000 9000 13000
Field oxide N+ OR P+
Figure 28.2 Variable via depth results from planarization. Reproduced from Brown (1986) by permission of IEEE
Multilevel Metallization 359
Wire 1 Wire 2
Ground PlaneJosephson Junction
Legend: Nb SiO2 Nb2O5 Junction Anodization
MoNx5W/sq. ResistorMo/ Al 0.15W/sq. Resistor
Figure 28.3 Multilevel metallization of a superconducting IC. Reproduced from Abelson and Kerber (2004), copyright2004, by permission of IEEE
O Si OCH3
O Si OC2H5CH3X 100~~
Figure 28.4 Structure of siloxane
28.2 Planarized MultilevelMetallizationTrue multilevel metallization starts at three levels ofmetal. Historically this occurred in the late 1980s whensubmicron CMOS technologies were introduced. In0.25 m technology up to six levels of metal are used inASICs and logic chips, three levels in memory chips. Inthe 45 nm technology generation there can be 10 levelsof metal.
A fully planar structure can be created when contact andvia holes are filled by CVD tungsten, and excess tungstenis removed, by etchback or by CMP (Figure 16.1). Thenumber of metal levels can be increased simply by re-peating the process over and over again because all levelsare planar, Figure 28.1.
Back-end process integration differs from that offront-end in the sense that the thermal budget concepthas a very different meaning. Whereas the front-endthermal budget is about the temperaturediffusion rela-tionship, the back-end thermal budget is about thetemperaturestress relation. For n-level metallizationthere will be 2n steps at 300400 C (for each layerCVD tungsten and PECVD oxide steps), with roomtemperature steps (etching, spin coating, CMP) inbetween. Stress, strain, adhesion, hillocks, voids andcracks have to be understood.
28.2.1 Contact/via plug
In order to get planarized metallization, CVD W-plug fillhas been adopted. Because CVD-W has excellent stepcoverage, the via hole will be completely filled. In orderto improve adhesion, a Ti/TiN adhesion layer is depositedbefore tungsten. Excess metal is etched or polished away,leaving a planar surface. The second metal (Ti/TiN/Al) isthen sputtered (Figure 28.5).
The SEM micrograph of Figure 28.6 shows the structureof a planarized multilevel metallization scheme. The topaluminum wiring levels are very planar. Tungsten has beenused for local interconnects (in the length scale 10 m).All dielectric layers have been etched away to reveal themetallization for analysis (e.g., for failure analysis).
360 Introduction to Microfabrication
Figure 28.5 Aluminum bottom metal with Ti/TiN/Wcontact plug after etchback (left) and with secondTi/TiN/aluminum metal layer (right)
Figure 28.6 Multilevel metallization with all dielectriclayers etched away. TiSi2/poly gates, tungsten plugs andlocal wires, Al global wires. Reproduced from Mann et al.(1995) by permission of IBM
When vias can be stacked on top of each other in a mul-tilevel metallization scheme, a lot of area can be saved,and freedom of wire routing increases. In Figure 28.6tungsten plugs can be seen on top of each other. The top-level plugs are somewhat larger than the bottom plugs,ensuring overlap. Misalignment is still there, but becausethe surfaces are planar, it does not lead to topographybuild-up.
28.3 Copper MetallizationAll ICs used aluminum for metallization till 1997, andmost still do, but copper was introduced into high-performance applications from the 0.25 m generationon. Copper resistivity is clearly smaller than that ofaluminum, 1.8 vs. 3 mohm-cm, and like aluminum, itis an exceptional material that thin film resistivity canbe very close to bulk value. However, copper has manydrawbacks and limitations. It diffuses rapidly in both
silicon and silicon dioxide, and new barrier materialshave to be invented. Copper cannot be plasma etched,so it has to be patterned by polishing (CMP). Copper isan impurity that is harmful for silicon transistors, so thewhole process line has to be designed to prevent copperfrom reaching silicon. This means that lithography,etching, CVD, etc., are duplicated for fabricatingfront-end and back-end.
Whereas aluminum deposition is always by sputteringand tungsten is by CVD, there are a number of copperdeposition methods available: namely, electroless, elec-troplating, CVD and sputtering. Sputtering is ruled outbecause of poor step coverage and inability to fill holes,but it can still be used to deposit a thin seed layer forelectrodeposition. Both CVD and electrodeposition meth-ods can fill the high aspect ratios encountered in deepsubmicron devices.
To eliminate copper diffusion into oxide, one solutionis to use non-oxide dielectrics, like nitride or polymers,but this is not without its problems. Nitride dielectric con-stant is fairly high (r 7) and polymers are not stableenough. As a compromise, oxide dielectric layers with ni-tride or carbide (SiC) barriers are used. These layers havean advantage in that they act as etch and polish stop lay-ers. The general issues of copper metallization are shownin Figure 28.7, and cross-sectional electron microscopeviews of a copper-filled via plug are shown in Figure 28.8.
Metallic barriers can be used to separate copper fromthe dielectric. Much studied choices include TiN, W:N,W:N:C, TaN and TaSiN. Metallic barriers are thin: for90 nm technology the barriers need to be below 10 nm.The resistivities of the barrier and plug are critical in the100 nm range because the full benefit of low-resistivitycopper cannot be realized if a high-resistivity barrier re-duces the effective resistivity of the plug. Barrier de-position is by for example ALD, which has excellentconformality. Seed layer deposition requirements are notas strict: thickness uniformity is not mandatory, only filmcontinuity. With more and more layers and materials, thenumber of materials interfaces is going up, and all theseinterfaces must be characterized for stability, reactions,diffusion, stresses, etc.
Polyimide is a very stable polymer and has been tried asthe intermetal dielectric in copper metallization. Copperis clad in tantalum barriers and polyimide is protected bynitride etch stop layers as shown in Figure 28.9. Copperis completely clad by either tantalum or nitride and neverin contact with the polyimide. Contact to silicon is stillmade by Ti/TiN/W plug, to prevent the danger of siliconcontamination.
CMP selectivity between copper and tantalum is veryhigh, which means that removal of tantalum leads to
Multilevel Metallization 361
General: low variation low particle generation large process window
t < 10 nm thick r < 500 W-cm Cl conc. < 2% unif. < 2% step coverage 3 nm/min
Low-k: CMP compatible Tdepo < 400 C adhesion on etch stopper
Copper seed t > 2 nm unif. < 2% step coverage ~100% rate > 10 nm/min growth and adhesion on etch stopper
Etch stopper: growth and adhesion on dielectric growth and adhesion on barrier
Figure 28.7 Copperlow-k metallization schematic for 90 nm technology. Adapted from Smith et al. (2002)
Figure 28.8 Copper via filling: left, with ALD TiN barrier; right, with ALD W:N:C barrier. Reproduced from Smithet al. (2002), copyright 2002, by permission of Elsevier
long overpolish times (cf. long overetch times). CMPnon-idealities, dishing and erosion have to be analyzed.Dishing is strongly linewidth dependent but ratherinsensitive to pattern density, whereas oxide erosion isvery strongly pattern density dependent and only mildlylinewidth dependent, as shown in Figure 28.10. CMPdishing and erosion in the 20 nm range are targeted for100 nm technologies.
28.4 Dual Damascene Metallization
Damascene metallization relies on etching via plugs inoxide, filling those plugs with copper, with CMP for re-moval of excess metal. In dual damascene this idea isdeveloped further. First, very thick oxide is deposited.Then, two lithography and two etching steps define viasand wires. Copper is then deposited and fills both the via
362 Introduction to Microfabrication
Figure 28.9 Cu/polyimide multilevel metallization withTa barriers, W plugs and silicon nitride polish stop layers.Reproduced from Small and Pearson (1990) by permissionof IBM
00 20 40 60 80 100
0 20 40 60 80 100
Pattern density (%)
Pattern density (%)
2 m5 m10 m20 m50 m100 m
5 m20 m50 m100 m
Figure 28.10 Dishing of copper and erosion of oxide.Source: Steigerwald J. M., et al, ChemicalMechanical Pla-narization of Microelectronic Materials, Wiley, 1997.This material is used by permission of John Wiley &Sons, Inc.
holes and the wires. CMP finishes the process as usual.This sequence is shown in Figure 28.11.
Dual damascene introduces novel process integrationfeatures. The thick dielectric consists of multiple layers:
namely, barriers/etch stops and the actual thicker filmswhich ensure electrical insulation. It is possible to makethe vias and trenches in four different ways, as shown inFigure 28.12:
1. Full via first (etching through the thick dielectric).2. Partial via first (etching halfway).3. Wire first (etching halfway).4. Partial wire first (etching a hard mask only).
Full via first (Figure 28.12a) is problematic because avery deep via hole of high aspect ratio is produced in thefirst step, making second photoresist spinning difficult.Additionally, the bottom hard mask needs to tolerate twoetch steps: it is exposed at the end of the via etch and allthe time during the trench (wire) etch. One solution is toprotect the bottom...