IO Blocks and Programmable Interconnection Points

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    18-Apr-2015

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<p>XILINX FPGA INPUT OUTPUT BLOCKS &amp; PROGRAMMABLE INTERCONNECTION POINTS</p> <p>XILINX FPGA-BASICS </p> <p>Field programmable gate array 2-D arrays cells separated by wiring channelsBasic structure: CLB - logic function generators IOB interface between IO pins &amp; internal logic PI connect CLB &amp; IOB1Programmable interconnections</p> <p>IO BLOCKS </p> <p>Interface between external package pins &amp; internal logic Configured as an input, output, or bidirectional port. D flip-flops are included to provided registered inputs and outputs. Direct and Registered inputs can be selected by Mux Three main signal paths within the IOB: input path Output path 3-state path Input path: Delay element can be set to ensure a hold time of zero Output path: Tri-state driver is present</p> <p>2</p> <p>IO BLOCKS</p> <p>3</p> <p>IO BLOCKS </p> <p>Output driver is active low enabled. D Flip Flop can be edge or level triggered Selectable polarity of signals from CLB using invertors CE is common to all FF CLK is separate for input and output Slew rate controlled to avoid noise Pull up and pull down used to connect unused IO to VCC or GRND</p> <p>4</p> <p>XILINX FPGA-INTERCONNECT</p> <p>Routing resources: wires &amp; switches (antifuse or pass transistors) Wire Segments: Wire unbroken by programmable switches Track: A sequence of one or more wire segments in a line. Routing Channels: group of parallel tracks (Horizontal channel or vertical channel)Switch boxwires</p> <p>Logic cellwires</p> <p>Logic cell</p> <p>Wire segment</p> <p>Horizontal channel</p> <p>Logic cell</p> <p>Logic cell</p> <p>Logic cell5</p> <p>Vertical channel</p> <p>GENERAL FPGA ROUTING ARCHITECTURE 1.</p> <p>2.</p> <p>The model contains two basic structures: Connection block : connects the inputs and outputs of a logic block to the wire segments in the channels. Switch block: provides connectivity between the horizontal as well as vertical wire segments. In some architectures, the switch block and connection block are intermingled, and in others they are combined into a single structure.</p> <p>6</p> <p>7</p> <p>General FPGA Routing Architecture</p> <p>INTERCONNECT - WIRES 1. 2.</p> <p>3.</p> <p>4. 5.</p> <p>Five types of wire segments: Global Clk: Clock inputs to CLBs Direct connect : between two adjacent CLBs Single groups: flexible connectivity between adjacent CLBs which pass through switch matrix Double groups: travel past 2 CLBs Long groups: span entire chips length or width</p> <p>8</p> <p>INTERCONNECT - WIRES</p> <p>9</p> <p>ROUTING RESOURCE WIRE SEGMENTS</p> <p>10</p> <p>CLB</p> <p>11 12</p> <p>PROGRAMMABLE INTERCONNECTSCLB 1 CLB 2 CLB 3</p> <p>CLB1</p> <p>CLB3</p> <p>CLB 4</p> <p>CLB 5</p> <p>CLB 6</p> <p>CLB9</p> <p>CLB 7</p> <p>CLB 8</p> <p>CLB 9</p> <p>12</p> <p>PROGRAMMABLE SWITCH MATRIXLong wires</p> <p>Horizontal channel</p> <p>Double length wires Single length wires</p> <p>Programmable Switch Matrix (PSM) is used to interconnect CLBs &amp; IOBs</p> <p>13</p> <p>ROUTING RESOURCE - PROGRAMMABLE SWITCH ELEMENTPSE</p> <p>PSM</p> <p>14</p> <p>ROUTING RESOURCE - PROGRAMMABLE SWITCH ELEMENT</p> <p>Programmable switch Element (PSE) connect to other lines For 4 lines, 6 possible pairwise connections can be formed 6 gates in each PSE</p> <p>15</p> <p>ROUTING RESOURCE - PIP</p> <p>PIP are programmable pass transistors that connects CLB inputs outputs to routing network</p> <p>16</p> <p>PROGRAMMING TECHNOLOGIES FOR SWITCH </p> <p>SRAM Programming Technology Antifuse Programming Technology Floating Gate Programming Technology</p> <p>17</p> <p>SRAM Programming Technology</p> <p>Static RAM cells to control pass gates or multiplexers</p> <p>Pass transistor For SRAM = 1, switch is closed For 0, switch is open</p> <p>MUX controls which one of the multiplexer inputs are connected to the output18</p> <p>SRAM Programming Technology</p> <p>Advantage: Fast reprogrammability Standard integrated circuit process technology Disadvantage: Large Area External Permanent memory required during power up</p> <p>19</p> <p>ANTIFUSE Programming Technology</p> <p>At the intersection of routing traces, a special contact is placed called an antifuse Unprogrammed state very high resistance between terminals Programmed state low resistance 11- 20 V and 5mA current is used for anitfuse programming</p> <p>Horizontal wire20</p> <p>Vertical wire</p> <p>ANTIFUSE</p> <p>3 sandwiched layers: conductors at top and bottom and an insulator in the middle. Antifuses consist of either of the following: ONO dielectric between N+ diffusion and poly-silicon Amorphous silicon between metal layers Amorphous silicon between polysilicon and the first layer of metal</p> <p>21</p> <p>ANTIFUSE Programming Technology</p> <p>Advantage: Small Size Relatively low series resistance and parasitic resistanceONO 300 to 500 ohm Amorphous si 50 to 100 ohm</p> <p>Disadvantage: One time Programmable External Pass transistor required during programming</p> <p>22</p> <p>Floating Gate Programming Technology </p> <p>UV erasable EPROM and EEPROM devices used Transistor Permanently disabled by injecting charge on floating gate</p> <p>24</p> <p>Floating Gate Programming Technology</p> <p>Advantage: Re-programmability No external permanent memory Disadvantage: High ON resistance High Static power consumption due to pull up resistor</p> <p>25</p> <p>Comparison of Programming Technologies</p> <p>26</p> <p>Programmable Interconnections FPGA layoutcell1 2 3 4 5</p> <p> Realized connectionscell1 cell2</p> <p>cell116 7 8 9 10</p> <p>cell5</p> <p>cell1027 11 12 13 14 15</p> <p>FPGA Programming</p> <p>An example of programming an FPGAx3f</p> <p>f1 x1 x2x1x1 x2</p> <p>x2</p> <p>0 0 0 1</p> <p>x2 f1 x3</p> <p>0 1 0 0</p> <p>f 2 x2 x3f2</p> <p>f x1 x2 x2 x3</p> <p>f1 f2</p> <p>0 1 1 1</p> <p>f3</p> <p>x1 LUT x2 0/1 0/1 0/1 0/1 f</p> <p>28</p> <p>REFERENCES</p> <p>Digital Design Principles and Practices John.F.Wakerly Architecture of FPGAs and CPLDs a tutorial Stephen Brown and Jonathan Rose www.xilinx.com</p>