Sensor design and mass test system development Y. Kwon (Yonsei Univ.) slide 0

Sensor design and mass test system development Y. Kwon (Yonsei Univ.)

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PowerPoint Sensor design and mass test system developmentY. Kwon(Yonsei Univ.)First real scale prototype chip from CERNOur involvementParticipation in chip design Preparation of mass test systemChip designChip design opportunitiesInteresting approach based on CIS technology Joint efforts with Prof. M. K. Song @ Dongguk Univ.2013-2014 : two master degree course students 2014-2015 : two doctorate degree course studentsStudent 1 : Daehyeok KimContinuation from 2013Involvement in front end development Student 2 : Sungjoo LeeNew involvementPast experiences in analog/digital circuits.Front end under studyInteresting featuresMass test systemIssue for the mass test system50k delicate pixel sensorsTest configurationProbe cardChuckTest definition : Laser, readout Automation (machine vision + robot, commercial solution available)To pick chips from tray, load them on chuck, test them according to the test configuration, and return to the holder.Minimum system to do custom chip test.Probe-cardPAD layoutTotal 103 pads to make contactTask 1, probe cardFPGACPUETHERNETSpecification1. 103 x 2 = 206 pins.3. 8 LEDs to check probe card position by eye.4. Contact status check at every 10 ms.5. Contact status report by ethernet.0. Dual pins for each pad Pin A for external connection (power/ground/IO), Pin B to check pin contact with the pad2. 14 + 3 relays as switches when we decouple pin A and pin B PAD sizeWe want dual pin contact for each pad.Probe needle layoutInvisibleChipProgramming optionComputer + ethernetSlow, but flexibleOn-board CPUIn-betweenFPGAFast, but limitedPin APin BInputAlgorithm to check contact Disconnect power/input using relay.Send 1.8(V) logic pulse to each digital input pad via pin A and read pin B.If no pair read back, raise chuck via .If any pair reads back, 3. Start careful adjustment . 4. Send 1.8(V) sequential logic pulse to other digital input pad via pin A and read pin B.Raise up until all input pad pairs read back.Send 1.8(V) sequential logic pulse to digital input pads via pin A and read pin B. (We will skip step 6 if we worry damage by electrical shock).7. Raise up until all input pad pairs read back.8. FPGA pull down for power pin B, FPGA pull up for ground pin B. 9. Disconnect FPGA output for pin A.10. Connect power.11. Check FPGA pin status12. Raise up until all pin B status is OK.13. Disconnect pin B for analog input. Use LED to display current status properly.FPGA flexibility enables variation of algorithm.ChuckTransparent chuck?Suction controlOne holeWould sensor be flat on the chuck?ProblemChuckVacuum holeChuckSensorSolutionMore small holes, air-tight chuckChucks in preparationWe are evaluating the optimal configuration.Test definition : Laser, readout Test definition?Basic elements are ready.Open chuck in page 24Laser (1000-1100 nm)?X-Y stage with optical maskRequires further communication with CERN StatusOptimization in progress with the delivery of proto type sensor.R&D in coordination with CERN --- We exchange experiences.

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