TTCS Tong Hop

  • Published on
    08-Jul-2015

  • View
    583

  • Download
    0

Embed Size (px)

Transcript

<p>Bin son : L Quc n -</p> <p>Thc tp c s</p> <p>BI 1 V S NGUYN L DNG ORCAD CAPTURE 9.2I. MC CHGip sinh vin tip cn vi phn mm h tr trong lnh vc thit k mch in t l Orcad 9.2. Phn mm gm 3 phn chnh: V s nguyn l (Schematic), m phng (Simulation) v v mch in (Layout). Do , cc bi 1, 2, 3, 4 c quan h mc xch vi nhau, sinh vin cn lu trong qu trnh thc hnh. V Schematic ca 1 s mch in. To th vin linh kin mi trong trng hp linh kin khng c trong danh sch th vin ca Orcad. To cc file Netlist Ch : Nhng vn chi tit v cch v sinh vin c th hc trong phn Learning Capture trong phn Help v s c dy trc tip trn my tnh.</p> <p>-</p> <p>II. V S MCH BNG ORCAD CAPTURE CIS1. Khi ng Orcad Capture CIS: Khi ng chng trnh Capture CIS to 1 s mi bng cch vo Start/ Programs/ Orcad Farmily Release 9.2/ Capture CIS. Chon Menu File/ New/ Project, khi xut hin hp thai New Project nh tn Project cn t vo Name. nh du chn vo: Analog or Mixed Signal Circuit Wizard ( nu mun dng Schematic m phng v v mch in), hoc Schematic (nu ch mun v mch n) Khi , s xut hin tip hp thai Creative Pspice Protect, chn 1 trong 2 ty chn v ni cn lu file project, ri nhn vo nt OK</p> <p>2. Cc bc c bn khi v Schematic: t linh kin: o Dng chut nhp vo nt Place Part trn thanh Toolbar hoc g phm P t bn phm. o Trong ca s Place Part g tn linh kin vo Part, nu khng tm thy linh kin, nhn nt Add Library b sung vo th vin. o Ch , nn chn ngun v mass phi ng nht chy m phng ng. o Mt s linh kin thng dng: Tn Part name Library in tr R analog.olb Khoa K Thut in T 2 1</p> <p>Bin son : L Quc n -</p> <p>Thc tp c s</p> <p>R_var analog.olb C analog.olb L analog.olb Q2N2222 bipolar.olb Q2N2907A bipolar.olb D1N4148 diode.olb LM741 opamp.olb VSIN source.olb VSRC source.olb 555B anl_misc.olb Sw_tclose anl_misc.olb Sw_topen anl_misc.olb o Trong qu trnh t linh kin, mun xoay linh kin th nhn R hay click phi chut ri chn chc nng xoay. Ni dy: o Dng chut nhp vo nt Place Wire trn thanh Toolbar, lc ny biu tng chut c hnh dng du cng, cho php ta ni cc chn linh kin li vi nhau. o Di chuyn chut ko di dy ni. o Click phm tri chut to 1 gc vung, v tip tc v. o Click phm phi chut, chn End Wire kt thc dy ni. o Nu ni b dy, nhn Place Bus trn thanh Toolbar v thc hin tng t, nhng ch l phi t Next Name trong cc dy trong b dy bng cch nhn nt Place Net Alias nh dng Text trong Schematic: o Nhn nt Place Text, th hp thai xut hin, nh vo dng Text cn thit ri chn OK Chn linh kin: o Nhn nt Select, sau dng chut chn linh kin. Chnh sa thng s ca linh kin: o Double Click ln gi tr ca linh kin. Khi , xut hin hp thai Display Properties, nhp gi tr mi vo Value, ri chn OK. o Cc k hiu n v (cho in tr, t in, in p, dng in, tn s,)</p> <p>Bin tr T in Cun dy Transistor NPN Transistor PNP Diode Opamp Ngun p SIN Ngun p DC IC555 Switch</p> <p>Khoa K Thut in T 2 -</p> <p>-</p> <p>2</p> <p>Bin son : L Quc n f ( femto) 10 15 p ( pico) 10 12 n(nano) 10 9 u (micro) 10 6 m(mili ) 10 3 k (kilo) 103 MEG (mega ) 106 G ( giga ) 109 T (tera ) 1012</p> <p>Thc tp c s</p> <p>Cch k hiu trn u nh nhau i vi ch hoa v ch thng Thay i thng s k thut ca Transistor, diode: o Trn Schematic nh du chn Transistor, diode ri Click phi chut chn Edit Pspice Model, khi xut hin hp thai Spice Mode. Ti y, ta thay i nhng thng s cn thit, sau ng ca s li. 3. Lu file sau khi v xong: Sau khi v xong, nu mun lu file vi tn c th chn nt Save. Trong trng hp mun lu file vi tn mi th vo File Save as v t tn file. File schematic l file c dng *.dsn</p> <p>III. TO FILE NETLIST:Sau khi v xong Schematic, trnh Layout v Pspice hiu c file.dsn th cn phi bin dch sang dng file Netlist tng ng. Chuyn sang ca s chnh (project manager), chn file hay page cn bin dch, chn Tool Create Netlist, lc ny ca s Create Netlist s hin ra v ta mun chn bin dch sang Layout hay Pspice th chn Tab tng ng v nhn OK. o Nu l Layout th cho ta file.mnl o Nu l Pspice th cho ta file.net Cc file ny s cha thng tin kt ni chn linh kin cng nh cc thng s k thut (nu l file.net).</p> <p>IV. TO LINH KIN V TH VIN MITrc tin to th vin cha linh kin bng cch mn hnh chnh ca Orcad Capture, chn File New Library, mn hnh Library xut hin. Mun i tn th vin th chn th vin hin hnh, click phi chut, chn Save as i tn. Khoa K Thut in T 2 - 3</p> <p>-</p> <p>Bin son : L Quc n -</p> <p>Thc tp c s</p> <p>To linh kin mi trong th vin bng cch t v tr th vin hin hnh, click phi chut chn New Part, hp New Part Properties xut hin, nh vo tn linh kin OK, mn hnh v linh kin xut hin. Trong mn hnh ny ta dng cc cng c: Place pin, place pin array, place text, place rectangle, to hnh dng theo yu cu Save trc khi thot.</p> <p>V. NI DUNG THC HNHBi 1: V s Schematic v chuyn sang Netlist cc mch sau : o Mch khuch i:Vcc Vin Vcc Vcc 12Vdc V1 VOFF = 0 VAMPL = 20mV FREQ = 50 Rc</p> <p>0</p> <p>0R1 Ci Vin 150k Q1</p> <p>4.7k Vout</p> <p>Q2SC1815 4.7u R2 15k Re 470 Ce 1u</p> <p>0</p> <p>o Mch ghp/tch knh ng b:</p> <p>Khoa K Thut in T 2 -</p> <p>-</p> <p>4</p> <p>Bin son : L Quc n Bi 2:</p> <p>Thc tp c s</p> <p>To linh kin c tn Led7 nh sau, ri lu vo th vin mylib-schematic.U1 LED 7 DOAN 3 R</p> <p>8</p> <p>K</p> <p>DP</p> <p>5</p> <p>-</p> <p>Np cc file thit k s nguyn l : *.sch; *.obj; *.dsn Np file thit k th vin</p> <p>Khoa K Thut in T 2 -</p> <p>7 6 4 2 1 9 10</p> <p>A B C D E F G</p> <p>led7</p> <p>-</p> <p>5</p> <p>Bin son : L Quc n -</p> <p>Thc tp c s</p> <p>BI 2 V S MCH IN DNG ORCAD LAYOUT PLUSI. MC CHGip sinh vin bit cch s dng chng trnh Orcad Layout Plus v s mch in trc tip hoc t s mch in c v bi Orcad Capture. Hng dn cho sinh vin cc bc c bn sau : Sp xp linh kin trn mch in sao cho hp l. V ng mch bng ch t ng hay bng th cng. Ti u ho cc ng mch in v kch thc mch in. Thay i cc thng s k thut cn thit trn board mch. To th vin mi v cc module linh kin mi.</p> <p>-</p> <p>II.1.</p> <p>HNG DN S DNG TRNH LAYOUT PLUSNp tp tin * .mnl : T ca s Orcad Layout chn New, xut hin ca s Load Template File, chn m tp tin Default.tch (cha thng tin v k thut v mch in). Sau khi m tp tin Default.tch, ca s Load Netlist Source xut hin cho php load tp tin cn v mch in ( *.mnl ). Bc tip theo chng trnh yu cu lu tn file cn v mch in (*.max). Nu th vin chn linh kin ca Layout c y theo s khi v schematic th sau khi lu thnh file *.max xong s xut hin ca s cha y chn linh kin ca schematic cn v, ngc li layout yu cu lin kt chn linh kin trong schematic cn v vi chn linh kin c trong th vin ca layout, hoc phi to chn linh kin mi.</p> <p>- 2. Sp xp linh kin : Khoa K Thut in T 2 6</p> <p>Bin son : L Quc n -</p> <p>Thc tp c s</p> <p>Sau khi tp tin *.max c y chn linh kin, bc tip theo ta cn b tr li v tr chn linh kin cho ph hp. t ng kim tra vic t linh kin c ng khng, chn menu Auto/Design Rule Check/Placement Spacing Violations . ng khung gii hn din tch mch in bng cch: vo menu Tools, chn Obstacle, chn tip Select Tool, s dng chut ko ng ng khung gii hn, ri chn End Command. Ch y : DRC cng cho php kim tra t ng cc yu t khc nh : vi phm khong v gia ng mch in vi nhau...</p> <p>-</p> <p>a) Sp xp linh kin t ng trn board : - Nhp chut vo menu Auto, chn Place, chn tip Board. b) t tng linh kin trn board : - Nhp chut tri vo bt k chn linh kin no s gn chn linh kin lin vi pointer ca chut cho php di chuyn t linh kin . - Layout cng cho php di chuyn mt nhm chn linh kin bng cch ko r chut tri ng khung nhm linh kin . - Sau khi chn linh kin gn vi pointer ca chut ta c th thc hin cc thao tc sau : Quay R ( n phm ) Kho linh kin L c) t nhm linh kin theo th t ch s : ( R1, R2...) Pop up menu bng cch nhp chut phi, chn Queue For Placement. Khi ca s Component Selection Criteria xut hin, nh R* vo RefDes ( Nu nhm linh kin l R1,R2...). Nhp OK. Pop up menu/Select Next, ln lt t linh kin cho n khi c thng bo, chn Cancel. 3. t kch thc board mch in - Chn Obstacle Tool v khung board mch in. 4. V ng mch xem cc thng s li ni gia cc chn linh kin s dng nt View Spreadsheet trn thanh Toolbar, sau chn Nets. Trong bng thng s ny ch cn ct Routing Enabled, nu t yes cho php v li, no th ngc li. chuyn i gia hai thng s ny, nh du cn chn, sau Pop up menu\Enable Disable. 7</p> <p>Khoa K Thut in T 2 -</p> <p>Bin son : L Quc n a. -</p> <p>Thc tp c s</p> <p> v c thun li, thc hin v li ngun v mass trc ( Gnd &amp;VCC net) sau mi v li tn hiu ( signal net ). Sau khi chn li v cn phi reset li vic chn c hiu lc, chn Window/Reset All. V t ng ( Auto route ) : Chn ch v ton board mch : Auto/Autoroute/Board. Chn ch v tng phn. View/Zoom DRC/Route Box. nh du khi cn v bng cch r chut ng khung. Auto/Autoroute/DRC/Route Box. V tay ( Manual route ) : Chn li cn v nh trn. n nt Add/Edit Route trn toolbar bt u v. Khi mun t corner (gc ngoc) th n nt chut tri. Khi mun t via ( xuyn lp ) th n V. Ch : y l cch v gia hai pad, mun v ghp hnh T, chn nt Show Track Mode trn thanh Toolbar. Chn lp ( Layers ) : Nhp nt View spread Sheet trn thanh Toolbar. Nu mun v 2 lp, ct Layer Type ca cc hng c gi tr l Routing ta i thnh Unused Routing ngoi tr 2 layer Top v Bottom ta gi nguyn, bng cch vo Pop up menu\Properties\Unused routing . Chn Window/Reset All.</p> <p>b. c. -</p> <p>-</p> <p>d. Sa ng mch : - Xa ng mch trn board dng ch Auto : Auto/Unroute/Board cho php xo ton b ng mch trn board hay Auto/Unroute/ DRC/Unroute Box cho php xo trong mt vng chn trc ( dng View/Zoom DRC/Route Box nh du vng cn xa). - Xa tng on : Nhp Edit Segment Mode trn Toolbar Nhp vo route cn xo , Pop up menu : Unroute segment cho php xa tng on. Unroute cho php xa ng mch gia 2 pad. - Unroute net : cho php xa ton b route c trong li ca route va chn. - Thay i kch thc ng mch: Nhp Edit segment mode trn thanh Toolbar. Khoa K Thut in T 2 8</p> <p>Bin son : L Quc n -</p> <p>Thc tp c s</p> <p>Nhp vo ng mch cn thay i, Pop up menu/ Change width v nh vo kch thc mong mun, nhp OK. 5. Ly linh kin mi - Chn nt Component Tool. - Click phi chut chn New mn hnh Add Component xut hin chn linh kin mi bng cch vo Footprint OK. 6. To th vin mi : - Chn Library Manager trn thanh toolbar. - Chn Create New Footprint , t tn v nhp OK. - Trn ca s Library Edit c sn mt pin chun, to pin mi : Chn nt Pin Tool trn thanh toolbar. Pop up menu/ New, (hoc nhp chut phi, n phm Insert), t pin ti v tr thch hp. Pop up menu/End Command. thay i cc thng s ca pin, Pop up menu/Properties. - t khung bao outline cho linh kin : Chn nt Obstacle trn thanh toolbar. Dng chut v outline. Pop up menu/Properties, chn Place Outline Obstacle Type. t outline ti v tr thch hp, Pop up menu/End Command. Save vo th vin. 7. Ph ng mch in : Chn Obstacle Tool New Properties Obstacle Type V d : Copper Poor l ph ton board mch Copper Area l ph theo vng Tip chn lp ph Obstacle Layer Net Attachment (mun NET no kt ni vi lp ph ng) -</p> <p>III. THC HNH TO TH VIN CHO LAYOUT1. Gii thiu th vin ca Layout TM - AXIAL : in tr. TM - CAP - P : in tr v t in. TM DIODE : Diode v Led cc loi. TO : Transitor. SIP : IC mt hng chn. 9</p> <p>Khoa K Thut in T 2</p> <p>Bin son : L Quc n -</p> <p>Thc tp c s</p> <p>-</p> <p>-</p> <p>- DIP100B : Cc IC dn. - DIP100T : IC khoan l. - DSUBJ : Cc cng giao tip my tnh DB9, DB25. - JUMPER : Jump 100,1000,1100,1200.... - RELAY : module relay. - LAYOUT : cc pad n. Trong qu trnh np tp tin netlist (c to sau khi v s mch) vo layout, kiu chn linh kin c chn khi v s mch khng c sn trong th vin ca Layout th ta phi to linh kin mi. iu quan trng nht trong qu trnh v mch in l phi bit hnh dng thc t ca linh kin v kiu v ca chng. Chng hn : transistor C1815 c kiu v l T092.</p> <p>2. Thc hnh to th vin cho layout</p> <p>To footprint cho led. To chn IC DIP8 (loi khoan l ). Sau khi to xong, lu vo th vin Mylib.llb IV. THC HNH V MCH IN 1. V mch in mt lp t mch khuch i sau - VCC</p> <p>I N</p> <p>-</p> <p>R 1 15 0k</p> <p>C 1 4. 7u</p> <p>-</p> <p>Q 1</p> <p>R 3 4. 7k Q2SC18 15</p> <p>-</p> <p>-</p> <p>R 2 1 5 k</p> <p>Khoa K Thut in T 2 -</p> <p>R 44 7 0</p> <p>-</p> <p>C 2 1 u</p> <p>-</p> <p>0</p> <p>-</p> <p>10</p> <p>Bin son : L Quc n V mch in hai lp t s mch ghp tch knh ng b trong bi 1 -</p> <p>Thc tp c s</p> <p>BI 3 - THIT K MCH IN CHO MCH KHUCH I CNG SUTI. MC CH Gip sinh vin thc hin c nhng mc tiu sau : - Thc hin cc cng on cn thit chuyn mt mch in t s nguyn l n mch in thc t. - Cch to cc th vin hoc nhng module cha c sn trong Orcad. - Hon chnh file mch in theo yu cu thc t t cc cng ty gia cng PCB. - Hon thin k nng s dng Orcad Layout Plus. II. NI DUNG THC HIN V li s nguyn l (nh lu li thc hin m phng mch bi sau) v chuyn sang mch in t s mch khuch i cng sut nh hnh v</p> <p>Khoa K Thut in T 2 -</p> <p>-</p> <p>11</p> <p>Bin son : L Quc n -</p> <p>Thc tp c s</p> <p>Mch in c cc thng s yu cu sau : Mch in hai lp : lp 1 (Top) l mt ghim linh kin v lp 2 (Bottom) l mt hn. Kch thc board mch : 2.5x2.5 (inch). Ph ng mt bottom. GND ni mch ph ng. Mt trn c ch thch hnh dng v gi tr linh kin. rng net ca 5V l 1mm, mc u tin l 100%. rng net ca GND l 0.5mm. rng cc net cn li cho bng 0.4mm. ng knh l khoan cc chn linh kin l 0.9mm. Cc thng s k thut khc theo tiu chun. mt ghim linh kin phi ghi (t lp SST): Tn : Nguyn Vn A Lp : 01VTA1 Nhm : 1 Bn : 01</p> <p>-</p> <p>Np file s nguyn l v PCB.</p> <p>Khoa K Thut in T 2 -</p> <p>-</p> <p>12</p> <p>Bin son : L Quc n -</p> <p>Thc tp c s</p> <p>BI 4 - M PHNG MCH KHUCH I DNG ORCAD PSPICE II. MC CH Xc nh v nh gi cc thng s ca mch khuch i: - im lm vic tnh, h s khuch i. - mo hi, p ng tn s. - Tr khng vo/ra II. M PHNG in: Cho mch in nh hnh v, s dng phn mm Orcad phn tch mchVCC VCC 12Vdc V1 R1 150k R3 4.7k Q1 Q2SC1815 4.7u V2 1Vac 0Vdc R2 15k R4 470 C2 1u</p> <p>0</p> <p>C1</p> <p>0</p> <p>0</p> <p>1. Xc nh im lm vic tnh (Bias Point). 2. Phn tch qu (Transient/ Noise): - V dng sng ng vo, ng ra ca mch. - Xc nh h s khuch i in p. - Xc nh mo hi ca mch khuch i. - Kho st nh hng ca ti. - Xc nh tr khng vo ra. Khoa K Thut in T 2 -</p> <p>-</p> <p>13</p> <p>Bin son : L Quc n 3. Thc hin phn tch AC (AC Sweep): - V p ng tn s ca mch. - Xc nh tn s ct di 3dB; tn s ct trn 3dB v bng thng. - Xc nh c tuyn pha tn ti ng ra ca mch. HNG DN :</p> <p>Thc tp c s</p> <p>-</p> <p>Bc 1: Khi ng chng trnh Capture CIS - v s mch. Thc hin nh sau: Vo Menu File/New/Project, khi xut hin hp thoi New Project, nh du chn vo Analog or Mixed Signal Circuit Wizard, nh tn Machkhuechdai. Nhp OK. Khi , s xut hin tip hp thoi Analog or Mixed Signal Circuit Wizard, nhp vo nt Finish. Ti y ta tin hnh v s mch theo yu cu bi. Bc 2: Khai bo cc thng s theo yu cu bi. Phn tch im phn cc tnh (DC Bias Point) Bc 3: chn ch phn tch: Phn 1 : -</p> <p>-</p> <p>-</p> <p>Trong Capture chuyn tr v file *.dsn, chn menu Pspice New Simulation Profile hin th hp thoi New Simulation. Trong hp thoi Name g vo ch Bias, hp thoi Inherit Form chn None sau click vo Create - Xut hin hp thoi Simulation Setting - Bias trn Analysis Type chn Bias Point OK . - T menu Pspice chn Run. Sau khi thc hin xong vic phn tch im phn cc th cc thng tin sau y s c thng bo trong file output - Danh sch cc nt in p - Dng ca cc ngun p v cng sut tng - Danh sch cc tham s tn hiu nh ca tt c cc linh kin Ti y ta thc hin xc nh im phn cc tnh ca mch in trn: ICQ = VCQ = IBQ = Xc nh li dng DC ca BJT: = ICQ/IBQ = Khoa K Thut in T 2 14</p> <p>-</p> <p>Bin son : L Quc n -</p> <p>Thc tp c s</p> <p>Thay i gi tr in p ngun Vcc = 9V. Xc nh li im lm vic tnh: ICQ = VCQ = IBQ = Xc nh li dng DC ca BJT: = ICQ/IBQ = Nhn xt v nhy ca im lm vic tnh i vi in p ngun, h s c ng theo l thuyt? - ............................................................................................................. - ............................................................................................................. - ............................................................................................................. - ..............................................</p>