Tong quan ve_fpga__1226

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  • 1. TRNG KHOA ----- ----- BO CO TT NGHIP ti: TNG QUAN V FPGA V NGN NG VHDL
  • 2. MC LC M u .............................................................................................................................1 CHNG 1 TNG QUAN V FPGA V NGN NG VHDL.................................2 1.1. Gii thiu v FPGA..........................................................................................2 1.2. Kin trc chung ca mt FPGA............................................................................. 3 1.3. Ngn ng phn cng HDL................................................................................5 CHNG 2 CC CNG C THIT K ..................................................................14 2.1. Nhng c im c bn ca XtremeDSP Development Kit-IV ........................ 14 2.2. Cc phn mm chuyn dng................................................................................. 23 2.3. Quy trnh thit k tng qut.................................................................................. 29 CHNG 3 GII THIU M HNH SOFTWARE DEFINED RADIO CHO H O TH KNH MIMO...............................................................................................32 3.1. Khi nim MIMO........................................................................................... 32 3.2. Lch s pht trin h MIMO................................................................................. 33 3.3. Nhng u im ca h MIMO............................................................................. 33 3.4. M hnh Software Defined Radio cho h o th knh MIMO .......................... 37 CHNG 4 KT QU THC NGHIM.40 4.1. C s l thuyt40 4.2. M hnh thit k.41 4.3. Kt qu m phng trn MATLAB.43 4.4. Kt qu thc nghim trn FPGA.......................................................................... 46 Kt lun............................................................................................................................ Ti liu tham kho ..........................................................Error! Bookmark not defined.
  • 3. M u Hin nay Thng tin v tuyn l mt ngnh pht trin rt mnh m, cc cng ngh s dng trong thng tin v tuyn ngy cng c i mi nhm nng cao tnh hiu qu trong iu ch, gii iu ch v truyn thng tin. Tuy nhin cng ngh pht trin cng cao th li cng t ra nhng kh khn trong vn thc nghim cho cc sinh vin trong cc trng i hc. Cc yu cu v phn cng i khi li tr thnh nhng th thch v cng phc tp trong vic a cc m hnh thit k vo thc t. V vy FPGA ra i nh mt gii php cung cp mi trng lm vic hiu qu cho cc ng dng thc t. Tnh linh ng cao trong qu trnh thit k cho php FPGA gii quyt nhng bi ton phc tp m trc kia ch thc hin nh phn mm my tnh. Ngoi ra, nh mt cng logic cao, FPGA c ng dng cho nhng bi ton i hi khi lng tnh ton ln v dng trong cc h thng lm vic theo thi gian thc. Trong s cc hng sn xut FPGA, Xilinx l mt trong cc hng i u trong vic sn xut chip, khng ch bi cc cng c h tr thit k hon thin m cn cho php ngi dng c kh nng can thip su vo h thng, trong phi k ti cc chip dng Virtex-sn phm mi nht ca Xilinx trong nhng nm gn y. Qua qu trnh tm hiu, nhm nghin cu thc hin c mt s cc ng dng trn FPGA nhm hng ti vic s dng FPGA nh mt cng c gii quyt bi ton o knh MIMO. y l vn thu ht c rt nhiu s quan tm ca cc nh nghin cu trong lnh vc truyn thng v tuyn. phc v cho mc ich ny, trong ni dung bi lun vn di y, em s trnh by v vic s dng FPGA thit k m hnh Software Defined Radio cho h o th knh MIMO.
  • 4. CHNG 1 TNG QUAN V FPGA V NGN NG VHDL 1.1. Gii thiu v FPGA FPGA l vit tt ca "Field Programmable Gate Array", l vi mch dng cu trc mng phn t logic m ngi dng c th lp trnh c, c th thc hin cc tnh nng logic thng qua my tnh ca mnh vi gi r, v c th xa i vit li nhiu ln. Xilinx l cng ty u tin bn ra FPGA v lun chim th phn ln nht. Ngoi ra cn c Alterna, Lattice, Actel, QuickLogic. Nhiu nh sn xut hin ang cung cp rt nhiu cu trc v phng php x l khc nhau. V vy, vic chn mt cu trc v mt phng php x l c th p ng c cc yu cu v chc nng v n nh, i vi mt h thng trong thc t l vn mang tnh quyt nh. Thit b logic lp trnh c c pht minh ln u vo cui thp k 1970 v ngay lp tc tr ln ph bin trong ngnh cng nghip bn dn. Ngoi kh nng lp trnh a dng, cng ngh ny cn c thi gian sn xut nh nn c kh nng cnh tranh thng mi rt ln. Hn na, vic thit k vi n kh d dng v n c kh nng lp trnh li nhiu ln. FPGA c thit k u tim bi Ross Freeman, ngi sng lp cng ty Xilinx vo nm 1984, kin trc mi ca FPGA cho php tnh hp s lng tng i ln cc phn t bn dn vo 1 vi mch so vi kin trc trc l CPLD (Complex Programmable Logic Device).im tng ng ca CPLD v FPGA l ch chng u bao gm mt s lng tng i ln cc phn t logic kh trnh. Tuy nhin mt tch hp th khc nhau, mt cng logic ca CPLD nm trong khong t vi nghn n hng chc nghn, trong khi vi FPGA th mt tch hp c hng chc nghn cho n vi triu. FPGA v CPLD c rt nhiu im khc bit tuy nhin kin trc l im khc bit chnh gia CPLD v FPGA. CPLD c kin trc gii hn mt mc no , n bao gm mt hoc nhiu di logic sum-of-products kh trnh v c cung cp mt s tng i nh cc thanh ghi c ng b. iu ny lm cho CPLD tr nn khng c mm do lm, nhng b li tr timing li d d on hn v tc kt ni logic cng cao
  • 5. hn FPGA. Vi FPGA, th kin trc theo mt cch khc tri hn hn CPLD bi v FPGA s dng cc lin kt ni. iu ny khng nhng to cho n mm do hn rt nhiu m cn lm tng phc tp trong tht k. im khc bit na gia FPGA v CPLD l trong hu ht chip FPGA u c cc hm cp cao (nh b cng v b nhn) v cc b nh c nhng vo. Ngoi ra, trong cc FPGA i mi cn h tr y hoc mt phn vic cu hnh li trong h thng, cho php thay i thit k tc l c th cp nht h thng hoc cu hnh ng (dynamic reconfiguration) khi chng ang hot ng nh l mt chc rt bnh thng. Mt vi FPGA cn c kh nng cu hnh li cc b (partial re-configuration) tc l mt phn ca thit b c cu hnh trong khi cc phn cn li vn ang hot ng. 1.2. Kin trc chung ca mt FPGA Cu trc tng th ca FPGA bao gm: -Cc khi Logic -H thng lin kt mch -Cc phn t tch hp sn Hnh 1.1 Cu trc tng th ca mt FPGA 1.2.1. Khi logic FPGA
  • 6. Hnh 1.2 Khi Logic FPGA cha trong n rt nhiu khi logic c th ti cu hnh CLB (Configurable Logic Blocks) c lin kt vi nhau thnh bng cc lin kt kh trnh (Programmable Interconnect). Cc khi vo ra c phn b xung quanh chip to thnh cc lin kt vi bn ngoi. Bn trong khi logic CLB c bng LUT (Look-Up Table) v cc phn t nh (FlipFlop hoc b cht). LUT (Look up table) l khi logic c th thc hin bt k hm logic no t 4 u vo, kt qu ca hm ny ty vo mc ch m gi ra ngoi khi logic trc tip hay thng qua phn t nh flip-flop. Trong ti liu hng dn ca cc dng FPGA ca Xilinx cn s dng khi nim SLICE, 1 Slice to thnh t gm 4 khi logic, s lng cc Slices thay i t vi nghn n vi chc nghn ty theo loi FPGA. Nu nhn cu trc tng th ca mng LUT th ngoi 4 u vo k trn cn h tr thm 2 u vo b xung t cc khi logic phn b trc v sau n nng tng s u vo ca LUT ln 6 chn. Cu trc ny l nhm tng tc cc b s hc logic. 1.2.2. H thng mch lin kt Mng lin kt trong FPGA c cu thnh t cc ng kt ni theo hai phng ngang v ng, ty theo tng loi FPGA m cc ng kt ni c chia thnh cc nhm khc nhau, v d trong XC4000 ca Xilinx c 3 loi kt ni: ngn, di v rt di. Cc ng kt ni c ni vi nhau thng qua cc khi chuyn mch lp trnh c (programable switch), trong mt khi chuyn mch cha mt s lng nt chuyn lp trnh c m bo cho cc dng lin kt phc tp khc nhau. 1.2.3. Cc phn t tch hp sn
  • 7. Ngoi cc khi logic ty theo cc loi FPGA khc nhau m c cc phn t tch hp thm khc nhau, v d thit k nhng ng dng SoC, trong dng Virtex 4,5 ca Xilinx c cha nhn x l PowerPC, hay trong Atmel FPSLIC tch hp nhn ARV, hay cho nhng ng dng x l tn hiu s DSP trong FPGA c tch hp cc DSP Slide l b nhn cng tc cao, thc hin hm A*B+C, v d dng Virtex ca Xilinx cha t vi chc n hng trm DSP slices vi A, B, C 18-bit. 1.3. Ngn ng m t phn cng (HDL) Ngn ng m t phn cng (HDL) l ngn ng lp trnh phn mm dng m hnh hat ng mong mun ca phn cng. C hai kha cnh m HDL to iu kin m t phn cng: m hnh hnh vi tru tng v m hnh cu trc phn cng. M hnh hnh vi tru tng. Ngn ng m t phn cng to iu kin d dng cho vic m t tru tng hnh vi ca phn cng i vi cc mc ch c t (ch r chi tit k thut). Hnh vi ny khng ch b chi phi bi cc kha cnh cu trc hoc thit k ca h phn cng. M hnh cu trc phn cng. Cu trc phn cng c kh nng c m hnh trong ngn ng m t phn cng m khng cn quan tm n hnh vi thit k. Nm 1980 b Quc phng M (DOD) mun thc hin vic thit k mch t dn chng, mun theo ui mt h phng php thit k tng qut v c th s dng li c vi cc cng ngh mi. R rng c nhu cu cho mt ngn ng lp trnh chun m t chc nng v cu trc ca cc mch s i vi vic thit k vi mch (IC). Sau DOD ti tr cho mt d n thuc chng trnh vi mch c tc rt cao VHSIC (very high speed integrated circuit) to ra ngn ng m t phn cng chun. Kt qu l d n ny to ra ngn ng m t phn cng VHSIC hay thng c gi l VHDL (VHSIC Hardware Description Language-Ngn ng miu t phn cng VHSIC) nh hin nay. VHDL c xem nh l s kt hp ca cc ngn ng sau : ngn ng tun t + ngn ng ng thi + netlist + nh thi + m phng. Do cu trc VHDL cho php th hin cch thc thc hin theo kiu song song hay tun t ca mt h thng s c hoc khng c timing. N cng cho php v m hnh mt h thng bng cc lin kt ni ca cc thnh phn.
  • 8. VHDL c dnh cho tng hp mch (synthesis) cng nh m phng mch (simulation). D VHDL c th m phng mt cch y , nhng khng p